Parallel programmable antifuse field programmable gate array...

Details Parallel programmable antifuse field programmable gate array... Parallel programmable antifuse field programmable gate array...

2007-08-13

2009-06-16

Whitmore, Stacy A (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C326S037000

Reexamination Certificate

active

07549138

ABSTRACT:
The present invention comprises apparatus and a method for simultaneously programming multiple antifuses in a multiple tile field programmable gate array (FPGA). The invention comprises an FPGA having a plurality of logic modules with programmable elements. The logic modules are partitioned into a plurality of individually programmable groups and an isolation device may be coupled between the individually programmable groups of logic modules such that each of the programmable elements in each of the plurality of individually programmable logic modules may be programmed concurrently.

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Copending U.S. Appl. No. 11/425,541, filed Jun. 26, 2006 entitled Repeatable Block Producing a Non-Uniform Routing Architecture in a Field Programmable Gate Array Having Segmented Tracks.
Copending U.S. Appl. No. 11/677,43

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