Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
1998-05-01
2001-09-25
Yoo, Do Hyun (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S003000, C711S147000, C711S124000, C711S122000
Reexamination Certificate
active
06295579
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a parallel processor system having a plurality of cache memories and a shared memory, and more particularly to such a parallel processor system in which the shared memory is constituted by plural distributed shared memories.
2. Description of the Related Art
Increasingly, improvements in parallel processor technology are focusing on communication among the processors to improve computer performance. Two primary communication means are the message passing method, in which processors exchange messages via a network, and the shared memory method, in which each processor accesses a shared memory.
Processors employing the message passing method generally exchange messages by starting an operating system. However, starting the operating system constitutes a large overhead, especially for communicating short messages.
In the shared memory method, on the other hand, communication may take place without starting the operating system. Therefore, the shared memory method alleviates this burden on communication.
A distributed shared memory method, which divides and distributes the shared memory, has proven to be an effective method for large-scale parallel processor systems. Distributing the shared memory allows simultaneous access to the shared memory by a plurality of processors, realizing a high level of parallel processing. An example of a distributed shared memory, in which nodes comprising a processor and a part of the shared memory are interconnected by a network, is disclosed in Japan Patent Laid-Open No. 89056/1993.
In this distributed shared memory method, when processors access the shared memory, data are transferred with high probability through the network. However, compared to the fast processing speed of the processors, the network speed is slow. Hence, the delay time through the network poses a problem for overall access speed.
A technique for speeding the access to a shared memory over a network provides a cache memory at each node. The cache memory is typically a small-capacity, high-speed buffer for registering the contents of part of the shared memory. Examples of distributed shared memories that use cache memory include Baylor et al, U.S. Pat. No. 5,313,609, and Lenoski et al, “The Stanford Multiprocessor,”
Computer
(March 1992), pp. 63-79.
These distributed shared memories that use cache memory are particularly characterized in that data in the shared memory in the same node (local data) and data in the shared memory in other nodes (remote data) are recorded in the same cache memory.
The distributed shared memory system divides large-scale array data and distributes them among the shared memory in each node. In array computations, each processor uses local data and remote data and performs calculations in parallel. The amount of remote data used in the array computation is generally enormous. Thus, when the large-scale array computation is performed by the distributed shared memory system that has the cache memory, the remote data used for the calculation cannot be fully accommodated in the cache memory, and are flushed out.
The local data includes, aside from the array data, those data which, though limited in quantity, are used the most often, such as a variety of system variables used by the operating system. Such data are desirably registered in the cache memory at all times to optimize overall system performance.
As stated above, remote data may be flushed from the cache memory when the capacity of the cache memory is insufficient for handling large-scale array computations. Similarly, the local data that is most frequently used may also be flushed out during large-scale array calculations due to the cache overflow resulting from accessing data at remote nodes. Loss of these frequently-used local data degrades the system performance.
SUMMARY OF THE INVENTION
The present invention solves this problem by controlling access to the distributed shared memory and to the plural cache memories to prevent frequently-used local data from being flushed out of a cache memory, which would otherwise occur due to cache overflow with remote data according to the systems described above.
The present invention includes, in a parallel processor system, a plurality of nodes each including a processor and a shared memory in a distributed shared memory arrangement, and a local-remote divided cache memory system, wherein local data and remote data are controlled separately. Each local-remote divided cache memory system includes a local data area, a remote data area, and a cache memory controller by which either the local data area or the remote data area is accessed according to the contents of an access request other constituent parts of the parallel processor system constructed according to the teachings of the present invention will be described in greater detail below.
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Akashi Hideya
Fujii Hiroaki
Sukegawa Naonobu
Tarui Tshiaki
Hitachi , Ltd.
Mattingly Stanger & Malur, P.C.
McLean Kimberly
Yoo Do Hyun
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