Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
1998-09-16
2001-07-17
Yoo, Do Hyun (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S121000, C711S124000, C712S029000
Reexamination Certificate
active
06263406
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to parallel processor systems in which a plurality of processors share a storage in common. More particularly, the present invention is directed to a parallel processor control method and system suited for synchronization control among processors that is based on interdependence between data in caches and data in the storage.
Synchronization control among a plurality of processors in a storage-shared parallel processor system includes start synchronization control that assures simultaneous start of all the processors, end synchronization control that assures the end of a process executed by each processor, and barrier synchronization control that assures storage access sequencing among the processors. Each processor has a cache for storing data copied from the storage, and when the processors process data on which they are dependent among themselves, the system must effect the start, end and barrier synchronization controls, considering coherency between the caches and storage (cache coherency).
How start, end and barrier synchronization instructions are processed serially in parallel data processing while maintaining coherency between cache data and storage data is the problem to be solved in improving parallel processing performance.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a parallel processor control method and system capable of assuring coherency between cache data and storage data by adjusting correspondence between the cache data and the storage data in executing synchronization instructions including start and end synchronization instructions or in executing a barrier synchronization instruction.
Another object of the present invention is to provide a high-speed cache synchronization mechanism by which storage controllers do not need to wait for cache entry cancel completion that assures coherency between cache data and storage data.
Still another object of the present invention is to provide a parallel processor control method and system capable of assuring high-speed cache-storage coherency by causing storage controllers to assure coherency between cache data and storage data using synchronization instructions including start and end synchronization instructions or using a barrier synchronization instruction.
Still another object of the present invention is to provide a parallel processor system capable of implementing hardware that treats a main processor and subprocessors equally by effecting start, end and barrier synchronizations using a single circuit and by assuring on a software basis that the main processor and the subprocessors perform the same operation.
Still another object of the present invention is to provide a parallel processor system capable of anticipating the start of a process using the data that is present in both caches and the storage by adding a synchronization interface bypassing cache-storage coherency assurance.
Still another object of the present invention is to provide a parallel processor system capable of implementing high-speed parallel processing by detecting a case where the absence of data dependence can be dynamically determined, effecting, upon detection of such a case, barrier synchronization independently of the completion of cache coherency control that assures cache-storage coherency, and thereby saving wait time.
Still another object of the present invention is to provide a parallel processor system capable of implementing high-speed parallel processing by detecting a case where the absence of data dependence can be dynamically determined, establishing, upon detection of such a case, a barrier synchronization independently of the completion of cache coherency control that assures cache-storage coherency, and thereby saving unnecessary wait time.
The present invention provides an apparatus for controlling parallel processors comprising:
a storage;
a plurality of processors respectively having caches and commonly sharing the storage; and
a plurality of storage controllers respectively connected to the plurality of processors, wherein
one of the plurality of processors has a start circuit for sending a start signal to the storage controller connected to the one processor when the one processor has executed a start instruction to the rest of the processors;
the storage controller connected to the one processor has a first assurance circuit for detecting completion of the sending of cache data cancel signals corresponding to a store instruction issued by the one processor before the start instruction and for notifying the storage controllers connected to the rest of the processors of the detection; and
the storage controllers connected to the rest of the processors have second assurance circuits for sending start instructions to the rest of the processors when the second assurance circuits detect completion of the issuing of cache cancel requests to the rest of the processors in response to the notification from the storage controller connected to the one processor.
It is possible to add an address management table for holding storage address information for data held in the caches; and
a cancel issuance circuit, connected to the first assurance circuit and the second assurance circuits for issuing said cache data cancel signals corresponding to a store instruction issued by the one processor by referencing the address management table. The rest of the processors stop processing subsequent instructions until the rest of the processors receive the start instructions. Further, the rest of the processors have end origination circuits for sending end signals to the storage controllers connected to the rest of the processors when the rest of the processors have executed end instructions each indicating that a process has ended; and
the storage controllers connected to the rest of the processors have circuits for detecting completion of the sending to the one processor of cache data cancel signals corresponding to a store instruction issued before the end instructions.
In another aspect of the present invention, it is possible to provide a storage-shared parallel processor system having a plurality of processors respectively having caches, a plurality of storage controllers (SC) respectively connected to the plurality of processors, a storage shared in common by the plurality of processors, and an address management table or front address array (FAA) for providing a centralized management of storage address information for data held in the caches of all the processors, wherein the parallel processor system comprises, to implement high-speed synchronization interface, a start interface including cache-storage coherency assurance. The start interface comprises: a circuit for causing a main processor to set a start register and send a start signal to an SC connected to the main processor when the main processor has decoded an instruction (start instruction) for starting subprocessors; a circuit for causing the SC connected to the main processor and having received the start signal to detect completion of an FAA check and of the issuing of a necessary cache cancel request corresponding to a store instruction issued before the start instruction and to notify the SCs connected to all the subprocessors of the detection; and a circuit for causing an SC connected to each subprocessor having received the notification to start the subprocessor connected to the SC when the SC has detected the issuing to the processor of all the cache cancel requests issued from the main processor to the subprocessor before the start instruction.
Further, the parallel processor system of the present invention comprises an end interface including cache-storage coherency assurance. The end interface comprises: a circuit for causing each subprocessor to set an end register and send an end signal to the SC connected to each subprocessor when each subprocessor has decoded an instruction (end instruction) indicating that an internal process has ended; a circuit for causing the SC c
Hashimoto Shigeko
Ichiki Tatsuya
Isobe Tadaaki
Miyaki Miki
Sukegawa Naonobu
Antonelli Terry Stout & Kraus LLP
Hitachi Ltd
Portka Gary J.
Yoo Do Hyun
LandOfFree
Parallel processor synchronization and coherency control... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Parallel processor synchronization and coherency control..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Parallel processor synchronization and coherency control... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2558596