Electrical computers and digital data processing systems: input/ – Access arbitrating – Decentralized arbitrating
Reexamination Certificate
2001-07-05
2004-10-26
Rinehart, Mark H. (Department: 2181)
Electrical computers and digital data processing systems: input/
Access arbitrating
Decentralized arbitrating
C709S253000, C710S112000
Reexamination Certificate
active
06810457
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a parallel processing system and a parallel processing method.
2. Description of the Related Art
As a high speed operation computer system like a supercomputer, a high speed parallel computer system is known in which one job is divided into a plurality of processes (tasks), and a plurality of processors cooperate and execute the tasks in parallel. Thus, a limit of performance improvement of a single processor can be overcome. A conventional parallel computer system called a perfectly distributed memory parallel computer system is composed of nodes connected by a dedicated network. Each of the nodes is composed of processors or CPUs, a memory, and a communication control unit (CCU). Communication between nodes is carried out via the network. Also, in recent years, a distributed sharing memory type parallel computer system (cluster type parallel computer system) is known in which the overhead for the parallel processing is less such as the easiness of the programming and internode data transfer. In such a parallel computer system, the node is composed of SMP (Symmetric Multiple Processor) and a communication control unit, and a memory is shared by a plurality of processors in the range with appropriate implementing cost.
In these distributed memory type parallel computer systems, the internode communication processing time is large, compared with a calculation processing time in the node. Therefore, the internode communication processing time transfer and the calculation processing are overlapped in the CPU, and an asynchronous communication instruction is completed when a CPU issues the asynchronous communication instruction. Thus, the communication processing time is concealed and the subsequent process and interrupt process can be executed without waiting for the completion of the asynchronous communication instruction.
Conventionally, a coprocessor is provided separately from a CPU, and communication processing is requested from a user program to an operating system (OS) by a system call from the viewpoint of hardware resource control, as in input/output processing. Thus, the communication processing is executed asynchronously from the CPU. However, this system call requires large software overhead so that the performance improvement of the parallel processing system is hindered.
For this reason, the technique is often adopted in which an asynchronous transfer instruction can be issued directly from the user program. When only the OS controls the asynchronous communication instruction, it is possible to ask the OS to control the asynchronous communication instructions such that the hardware resources are not fully consumed. However, when the asynchronous transfer instructions is issued directly from the user program, a flow control of the asynchronous transfer instructions is necessary to protect the system from the system performance degradation due to the hardware resource control overhead.
Conventionally, as such a flow control, a hand-shaking system is known in which when the CCU receives an asynchronous communication request from the CPU, the CCU notifies the reception of the request to the CPU. When a hand-shaking reply is notified, the CPU interprets the hand-shaking reply as the completion of the asynchronous communication instruction and starts the issuance of a subsequent instruction and an interruption process.
In the hand-shaking system, as shown in
FIGS. 8 and 9
, when a request buffer of the CCU
101
is full, the CCU
101
does not return the hand-shaking reply to the CPU
102
until the entry is ensured in the request buffer (Steps S
102
,
103
and
104
). Since the asynchronous communication instruction does not complete, the CPU cannot release an interrupt prohibition state. Therefore, there is a problem that the use efficiency of the CPU is reduced remarkably. Especially, in the parallel computer system which several hundreds of nodes are connected via an interconnection network, it is expected that it takes a very long time until an entry is ensured in the request buffer depending on the communication state on the interconnection network.
In conjunction with the above description, a communication control apparatus is disclosed in Japanese Laid Open Patent application (JP-A-Heisei 2-64838). In this reference, a plurality of communication control apparatuses are connected to a host apparatus. The communication control apparatus is composed of a reception buffer receiving and temporarily storing data in accordance with an instruction from the host apparatus. A first section sets a reception buffer full notice flag when reception data are stored in the reception buffer more than a first predetermined quantity, and resets the reception buffer full notice flag when the reception data are stored in the reception buffer less than a first predetermined quantity which is less than the first predetermined quantity. A flag setting section checks the reception buffer full notice flag when transmitting a transmission frame in response to a transmission instruction from the host apparatus, sets a predetermined bit to “1” of a control section of the transmission frame when the flag is set, and to “0” when the flag is reset, and transmits the transmission frame. A second section receives the transmission frame, sets the reception buffer full notice flag when the predetermined bit of the control section is set to “1”, and resets the reception buffer full notice flag when the predetermined bit of the control section is set to “0”. A report section checks the reception buffer full notice flag when a transmission instruction is received from the host apparatus, do not receive transmission data from the host apparatus when the flag is set, and reports that the data are stored in the reception buffer more than the first predetermined quantity.
Also, a communication control system is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 4-18500). In this reference, the communication control system is composed of a plurality of communication units communicating with each other. The control unit is composed of a communication control section connected to a transmission path and a main control section communicating with the other communication units via the communication control unit. A first reception buffer is provided to store reception data to the main control section, and a second reception buffer is provided to store reception data to the communication control section. A common memory is provided for the main control section and the communication control section. The main control section sets a reception stop flag to the common memory when the first reception buffer is full. The communication control section stores the reception data in the second reception buffer depending on the reception stop flag. The communication control section transmits a transmission stop signal when the second reception buffer is full and sets a transmission stop signal transmission flag. The transmission control section sets a first transmission stop flag to the common memory when the transmission buffer is full. The main control section stops sending of the transmission data to the communication control section depending on the first transmission stop flag. The main control section resets the reception stop flag when the first reception buffer is not full, and sends an interrupt signal to the communication control section. The communication control section transfers the data from the second reception buffer to the first reception buffer in response to the interrupt signal. The communication control section transmits a transmission permission signal when the reception stop flag is reset and the transmission stop signal transmission flag is set. When a transmission stop signal is received from another unit, the communication control section is sets the second transmission stop flag and stops the transmission of the transmission data to the other unit. When the transmission permission signal is receive
Knoll Clifford
NEC Corporation
Rinehart Mark H.
Young & Thompson
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