Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2005-04-12
2005-04-12
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C708S492000
Reexamination Certificate
active
06880121
ABSTRACT:
A syndrome polynomial calculating circuit and a Reed-Solomon decoding circuit capable of performing a high-speed operation. Higher-order signals I1,I2and I3are inputted to first to third Galois field multiplication circuits. For each of S0,S1,S2and S3,the multipliers are a6, a9, a12; a2, a4, a6, a8; a, a2, a3, a4. Outputs of first to third multiplication circuits and I4are sent to an exclusive-OR gate, an output of which is sent to a D-F/F. An output of the D-F/F is sent to a fourth Galois field multiplication circuit and to an AND gate. For each of S0,S1,S2and S3, multipliers of the fourth multiplication circuit are a4, a8, a12, a16. An output of the fourth multiplication circuit is sent to a fifth input of the exclusive OR gate. Clocks are input to the D-F/F and to a counter. The counter value is reset by the inputting of a frame pulse. The counter value is L or H for the counter value of 0 to 4 or 5, respectively. A counter output is sent to the AND gate. A signal from the D-F/F is outputted only if the signal is H.
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Britt Cynthia
De'cady Albert
Foley & Lardner LLP
NEC Corporation
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