Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2005-02-22
2005-02-22
Lamarre, Guy J. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S756000, C714S782000
Reexamination Certificate
active
06859905
ABSTRACT:
In a parallel processing Reed-Solomon encoding circuit that allows an arbitrary parallel processing number to be taken and the parallel processing number optimal to the system to be adopted, the multiplier factors corresponding to the first inputs of the first Galois field product sum circuit to the fourth Galois field product sum circuit are the zeroth to third order coefficients of the generator polynomial G(x). The multiplier factors corresponding to the second inputs are the zeroth to third order coefficients of a polynomial of a remainder from x5divided by the generator polynomial G(x). The multiplier factors corresponding to the third inputs are the zeroth to third order coefficients of a polynomial of a remainder from x6divided by the generator polynomial G(x).
REFERENCES:
patent: 5912905 (1999-06-01), Sakai et al.
patent: 6405339 (2002-06-01), Cox et al.
patent: 11-136136 (1999-05-01), None
patent: 11136136 (1999-05-01), None
patent: 11-298447 (1999-10-01), None
Hideki Imai, Japan Engineering Technology Center, “Error Correction Encoding Techniques”, p. 30, 1986.
Lamarre Guy J.
NEC Corporation
Young & Thompson
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