Parallel processing apparatus based on arbitrary determination o

Details Parallel processing apparatus based on arbitrary determination o Parallel processing apparatus based on arbitrary determination o

1994-03-31

1996-07-02

Coles, Sr., Edward L.

Facsimile and static presentation processing

Facsimile

Specific signal processing circuitry

358452, 358448, 358462, 358538, 382176, 382304, H04N 1387, H04N 140, H04N 146, G06K 940

Patent

active

055328431

ABSTRACT:
When determining areas, a data for determining area Ds, including bit data D.sub.0 which shows whether the area to be processed or not, is stored in a frame memory for determining area 5. When carrying out image processing, the frame memory 5 outputs the data Ds in synchronization with the output of image data D form a A/D converter 3. A gate 4 outputs the image data D only when the bit data D.sub.0 is a value [1] representing the area to be processed. In Synchronization with the output of the data D, bit sequence D.sub.1 .about.D.sub.n is output as the additional data regarding to the area. In an image processing system(not shown), although the image processing is carried out for the whole of a frame memory, the image data D is not supplied except for the area shown by the bit data D.sub.0 so as not to be carried out the image processing. Therefore, only for the area shown by the bit data D.sub.0, the image processing is carried out in accordance with the bit sequence D.sub.1 .about.D.sub.n.

REFERENCES:
patent: 4984283 (1991-01-01), Sakano
patent: 5140440 (1992-08-01), Sasaki
patent: 5351138 (1994-09-01), Sasaki et al.
patent: 5465307 (1995-11-01), Azumaya et al.

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