Parallel process address generator and method

Details Parallel process address generator and method Parallel process address generator and method

1997-04-03

1998-07-07

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

For multiple memory modules

711217, G06F 1200

Patent

active

057784167

ABSTRACT:
A memory linked address generator and method for a complex arithmetic processor executing an algorithm sequence includes memories, a clock for generating a clock cycle, and a decoder for determining position of the complex arithmetic processor within the algorithm sequence. The decoder is coupled to the clock and address pointer generators are coupled to the decoder and to the memories. The address pointer generators generate address pointers within the clock cycle for at least some of the memories in response to the position of the complex arithmetic processor within the algorithm sequence.

REFERENCES:
patent: 3731284 (1973-05-01), Thies
patent: 3871577 (1975-03-01), Avellar et al.
patent: 4893279 (1990-01-01), Rahman et al.
patent: 4920480 (1990-04-01), Murakami et al.
patent: 4974188 (1990-11-01), Dolecek
patent: 5012441 (1991-04-01), Retter
patent: 5029079 (1991-07-01), Magar et al.
patent: 5032986 (1991-07-01), Pathak et al.
patent: 5045993 (1991-09-01), Murakami et al.
patent: 5109497 (1992-04-01), Bolstad et al.
patent: 5224063 (1993-06-01), Matsunaga
patent: 5307300 (1994-04-01), Komoto et al.
patent: 5341485 (1994-08-01), Hattersley et al.
patent: 5430667 (1995-07-01), Takano
patent: 5450553 (1995-09-01), Kitagaki et al.
patent: 5475828 (1995-12-01), Goto
Zobel, R.N., "Some Atternative Techniques for Hardware Address Generators for Digital Signal Processors", 1988 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No. 88CH2458-8), pp. 69-72, vol. 1.
An article entitled "LH9320 DSP Address Generator" from Sharp Data Sheet, (FDS-Rev. A, Sep. 30, 1992).
An article entitled "LH9124 Digital Signal Processor" from Sharp Data Sheet, (Ref. Code SMT90033 Jul. 1992).
An aricle entitled "Frequency Domain Array Processor , A66540A/4K, 16K, 64K, A66540B/4K, 16K, 64K", from Preliminary User's Guide, Revision 3/91(Array Microsystems, 1420 Quial Lake Loop, Colorado Springs, CO 80906).
An article entitled "A 300-MOPS Video Signal Processor with a Parallel Architecture" by Toshihiro Minami, Ryota Kasai, Yamauchi, Yutaka Tashiro, Jun-ichi Takahashi and Shigeru Date, from IEEE Journal of Solid-State Circuits, vol. 26, No. 12, (Dec. 1991).

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