Parallel precoder circuit

Details Parallel precoder circuit Parallel precoder circuit

2008-09-23

2008-09-23

Chaudry, Mujtaba K. (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C341S076000, C341S143000

Reexamination Certificate

active

11349248

ABSTRACT:
A parallel precoder circuit executes a differential encoding operation on an n-row parallel input information series, and outputs an n-row parallel output information series, where 2≦n. Output sets of differential encoding operation circuits each of which having a largest column number from among differential encoding operation circuits disposed in first row to (n−1)th row become first-row to (n−1)th-row parallel outputs information series, and an output set of an nth-row delay circuit becomes nth-row parallel output information series.

REFERENCES:
patent: 4486739 (1984-12-01), Franaszek et al.
patent: 4618955 (1986-10-01), Sharpe et al.
patent: 6456208 (2002-09-01), Nazari et al.
patent: 6753797 (2004-06-01), Bliss et al.
patent: 6920604 (2005-07-01), Coakeley et al.
patent: 2005/0012534 (2005-01-01), Konczykowska et al.
patent: 2005/0135816 (2005-06-01), Han et al.
patent: 2006/0002714 (2006-01-01), Gill et al.
patent: 2004-140744 (2004-05-01), None
M. Serbay, et al., “Implementation of differential precoder for high-speed optical DQPSK transmission”, Electronics Letters, vol. 40, No. 20, Sep. 30, 2004, pp. 1288-1290, cover page and table of contents.

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