Parallel parity checking for content addressable memory and...

Details Parallel parity checking for content addressable memory and... Parallel parity checking for content addressable memory and...

2005-08-18

2009-08-04

Chaudry, M. Mujtaba K (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S800000

Reexamination Certificate

active

07571371

ABSTRACT:
Methods and arrangements for parallel parity checking for content addressable memory and ternary content addressable memory during compare cycles are disclosed. Further, methods and arrangements for remedying storage bit corruption are also disclosed.

REFERENCES:
patent: 4755974 (1988-07-01), Yamada et al.
patent: 5043943 (1991-08-01), Crisp et al.
patent: 5053991 (1991-10-01), Burrows
patent: 5111427 (1992-05-01), Kobayashi et al.
patent: 5130945 (1992-07-01), Hamamoto et al.
patent: 5233610 (1993-08-01), Nakayama et al.
patent: 5258946 (1993-11-01), Graf
patent: 5311462 (1994-05-01), Wells
patent: 5491703 (1996-02-01), Barnaby et al.
patent: 5699346 (1997-12-01), VanDervort
patent: 5796758 (1998-08-01), Levitan
patent: 6597595 (2003-07-01), Ichiriu et al.
patent: 2004/0083421 (2004-04-01), Foss et al.
“Data Corruption Scrubbing For Content Addressable Memory and Ternary Content Addressable Memory”, Wickeraad, John et al., Filing Date Aug. 18, 2005, (Serial No. Unassigned).

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