Parallel memory device rank selection

Details Parallel memory device rank selection Parallel memory device rank selection

2011-08-09

2011-08-09

Thomas, Shane M (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S005000

Reexamination Certificate

active

07996602

ABSTRACT:
A translator of an apparatus in an example selects one or more ranks of parallel memory devices from a plurality of available ranks of parallel memory devices in a plurality of double data rate registered and/or unbuffered dual in-line memory modules (DDR registered and/or unbuffered DIMMs) through employment of a native fully buffered dual in-line memory module protocol (native FB-DIMM protocol).

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JEDEC STANDATD, FBDIMM: Architecture and Protocol, JESD206.PDF© JEDEC Solid State Technology Association 2007, Arlington, Virginia http://www.jedec.org/download/search/JESD206.pdf Section 2.1.3 (AMB addressing) table 2-4 showing the DS [3:0] usage.
Same Document Section 2.1.3 paragraph 3 shows that for DRAM addressing one can only use DS [2:0].
Same Document Section 4.2.3 find the FBD command encoding protocol. This is the same protocol that would be used by disclosure 63, this table also shows the RS (rank selection bit).
Same Document Section 4.2.4 find information on DRAM commands and a DRAM comman mapping example—this section (paragraph 3) explains the use of the RS bit according to the FBD spec.
Same Document Section 4.4.2 gives a write timing example and describes the use of write FIFOs by the AMB.
Same Document Section 4.4.2.1 describes the use of the WS bits according to the FBD protocol.
Torres, Gabriel “How FB-DIMM Memories Work”, http://www.hardwaresecrets.com/article/266, published Dec. 23, 2005.

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