Parallel LDPC decoder

Details Parallel LDPC decoder Parallel LDPC decoder

2011-04-26

2011-04-26

Baderman, Scott T (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

Reexamination Certificate

active

07934139

ABSTRACT:
An LDPC decoder that implements an iterative message-passing algorithm, where the improvement includes a pipeline architecture such that the decoder accumulates results for row operations during column operations, such that additional time and memory are not required to store results from the row operations beyond that required for the column operations.

REFERENCES:
patent: 7000177 (2006-02-01), Wu et al.
patent: 2004/0240590 (2004-12-01), Cameron et al.
patent: 2008/0282127 (2008-11-01), Mantha et al.
Shimizu, K, A parallel LSI schitecture for LDPC decoder improving message-passing schedule, Sep. 2006, IEEE, pp. 5100-51-1.

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