Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2007-03-06
2007-03-06
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S796000
Reexamination Certificate
active
10709099
ABSTRACT:
A P-tap parallel decision-feedback decoder (PDFD) is also disclosed. The PDFD includes a plurality of state shift registers. For each state of a code utilized by an incoming data stream, a survivor metric for a state is shifted into the first shift register for the state. Each first shift register has M cells. A decision device is coupled to the first shift registers for outputting a first survivor metric according to survivor metrics in the first shift registers. A second shift register has N delay cells, and the first survivor metric is shifted into the second shift register.
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Erich F. Haratsch; A 1-Gb/s Joint Equalizer and Trellis Doceder for 1000BASE-T Gigabit Ethernet; IEEE Journal of Solid-State Circuits; March 2001; p. 374-p. 384; vol. 36, No. 3.
Ho Jung-Feng
Kuo Shieh-Hsing
Lin Hou-Wei
Yen Kuang-Yu
Alphonse Fritz
De'cady Albert
Hsu Winston
Realtek Semiconductor Corp.
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