Parallel data transfer circuit

Details Parallel data transfer circuit Parallel data transfer circuit

1994-02-23

1995-05-16

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Parallel read/write

365 78, 36518912, G11C 700

Patent

active

054167450

ABSTRACT:
A parallel data transfer circuit wherein processing at a data transfer source circuit is simplified to reduce the time required for transfer and a data storage area of a data transfer destination circuit can be used effectively is disclosed. A plurality of data register sets for temporarily latching parallel data and a plurality of corresponding flag register sets are provided between a data transfer source circuit and a data transfer destination circuit. A register designation signal is outputted from the data transfer source circuit to designate a data register into which data should be written. Only when data should be written into the data register, a flag is placed into a corresponding flag register. Since the data transfer destination circuit fetches data only from those data registers corresponding to those flag registers in which a flag is held, parallel data can be received without forming a discontinuous empty portion in data storage area of the data transfer destination circuit.

REFERENCES:
patent: 5257237 (1993-10-01), Aranda
patent: 5282164 (1994-01-01), Kawana

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