Parallel data scrambler

Cryptography – Particular algorithmic function encoding – Public key

Reexamination Certificate

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Details

C380S210000, C380S255000, C380S265000, C380S259000

Reexamination Certificate

active

07106859

ABSTRACT:
A data scrambler is capable of scrambling N bits of data in parallel using a 2B−1 bit scrambling sequence. The scrambler may store scrambling values of an m-sequence in a table. The table may be formed into at least two overlapping swaths of N columns, wherein each swath may store the m-sequence and the m-sequence of one swath is shifted from the m-sequence of a second swath. The scrambler may read a current swath N bits at a time and then may scramble N bits of input data in parallel using the N bits of the swath. When the swath is finished, the scrambler may shift to another swath.

REFERENCES:
Applications of sequence space and SRG theories to distributed sample scrambling; Seok Chang Kim; Byeong Gi Lee; Communications, IEEE Transactions on vol. 45, Issue 9, Sep. 1997 pp. 1043-1052.
Implementation of parallel DSS for cell-based ATM physical layer; Kim et al. ; SUPERCOMM/ICC '94, Serving Humanity Through Communications. IEEE International Conference on May 1-5, 1994 pp. 1359-1363 vol. 3.
Integrated parallel scrambler design for high-speed transmission systems; Lee, S.H.; Lee, P.J.; Circuits and Systems, 1988., IEEE International Symposium on Jun. 7-9, 1988 pp. 361-364 vol. 1.
Sang, H. Lee et al, “Integrated Parallel Scrambler Design For High-Speed Transmission Systems”,ISCAS 1988, pp. 361-364.

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