Parallel data outputting storage circuit

Details Parallel data outputting storage circuit Parallel data outputting storage circuit

1994-06-28

1996-03-19

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Sipo/piso

365220, 365221, 365236, 365239, G11C 700

Patent

active

055008259

ABSTRACT:
A plurality of delay time data can easily be obtained. A data input unit 32 successively writes data into a memory 30. A data output unit 36 outputs data from six areas a-f in the memory 30 in the parallel manner. Selection units SW1 and SW2 successively select and output data read out from the six areas a-f in the memory 30. Locations to be read are shifted from one another by the selection units SW1 and SW2 to output data from different memory locations. Thus, a plurality of data which are different in time between write and readout operations (i.e., different delay times) can be obtained simultaneously.

REFERENCES:
patent: 4171538 (1979-10-01), Sheller
patent: 4237343 (1980-12-01), Kurtin et al.
patent: 4389915 (1983-06-01), Bione
patent: 4549283 (1985-10-01), McDermott
patent: 4611299 (1986-09-01), Hori et al.
patent: 4710966 (1987-12-01), Aufiero
patent: 4873667 (1989-10-01), Geadah et al.
patent: 4945518 (1990-07-01), Muramatsu et al.
patent: 5280448 (1994-01-01), Watanabe

Affiliated with

Also associated with

Rating

Parallel data outputting storage circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Parallel data outputting storage circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Parallel data outputting storage circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1962995