Parallel data bus with bit position encoded on the clock wire

Details Parallel data bus with bit position encoded on the clock wire Parallel data bus with bit position encoded on the clock wire

2005-05-03

2005-05-03

Gaffin, Jeffrey (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Peripheral adapting

C710S035000, C710S061000, C710S066000, C710S071000, C713S500000, C713S503000, C713S600000

Reexamination Certificate

active

06889272

ABSTRACT:
A system and method for transmitting parallel data from a source to a destination over a plurality of high speed serial lines operates reliably even in the presence of data skew. The high speed data transmission system includes a protocol generator, a de-skew circuit, and a plurality of high speed serial lines coupled between the protocol generator and the de-skew circuit. Respective serial representations of parallel data words are transmitted to the destination over a plurality of serial data lines, and a clock signal is transmitted to the destination over a clock line in parallel with the serial data lines. The clock signal has at least one data bit of each parallel data word encoded thereon. The de-skew circuit aligns regenerated parallel data words using the respective data bits encoded on the clock signal to eliminate skew among the data bits, and regenerates the parallel data from the aligned parallel data words.

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patent: 6560275 (2003-05-01), Lecourtier et al.

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