Parallel cyclic redundancy code error detection

Details Parallel cyclic redundancy code error detection Parallel cyclic redundancy code error detection

1996-10-30

1999-01-12

Chung, Phung M.

Excavating

371 48, G06F 1110, H03M 1300

Patent

active

058598596

ABSTRACT:
An error detection circuit and method for detecting errors in data using a cyclic redundancy code which includes a plurality of first EXCLUSIVE OR gates each of which receives one bit of input data and one bit of a first portion of remainder data. Each first EXCLUSIVE OR gate outputs the EXCLUSIVE OR of the input data bits and the first remainder data bits to a corresponding one of a plurality of first registers to provide input data to the registers such that the registers store the result of the EXCLUSIVE OR operation. Each of a plurality of second EXCLUSIVE OR gates receives the output of a corresponding one of the plurality of first registers and receives one bit of a second portion of remainder data. Each second EXCLUSIVE OR outputs the EXCLUSIVE OR of these two inputs to a corresponding one of a plurality of second registers which store this second result. Each of the second registers has an output for outputing their stored value.

REFERENCES:
patent: 5408476 (1995-04-01), Kawai et al.

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