Parallel CRC formulation

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction

Reexamination Certificate

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C714S758000

Reexamination Certificate

active

07047479

ABSTRACT:
A system and method that calculates multiple bytes of data in a single cycle. The invention uses at least two CRC circuits to calculate a CRC value for a string of data. A first CRC circuit is used for calculating multiple bytes at a time. A second CRC circuit is used for calculating a single byte. The first CRC circuit is only used when there are multiple bytes to be processed. If there are other CRC circuits, then data is directed to the appropriate CRC circuit, i.e., the CRC circuit that calculates the appropriate number of bytes, when the number of bytes remaining to be processed is less than the first CRC circuit can process. Otherwise, the data is directed to the second CRC circuit, and must be processed one byte at a time until there is no more data remaining.

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patent: 5282215 (1994-01-01), Hyodo et al.
patent: 6530057 (2003-03-01), Kimmitt
patent: 6675236 (2004-01-01), Moon et al.
Scott, “Understanding Cyclic Redundancy Check,” Mar. 1999, pp. 1-14.
“Modular Arithmetic,” © 1996-2001 Alexander Bogomolny, pp. 1-4.
Barr, “Easier Said Than Done,” © 2000 Miller Freeman, pp. 1-11.
Barr, “Checking Up,” © 1999 Miller Freeman, pp. 1-8.
Barr, “Strength in Numbers,” © 1999 Miller Freeman, pp. 1-6.
Perez, “Byte-wise CRC Calculations,” IEEE Micro, Jun. 1983, pp. 40-50.

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