Parallel configuration of programmable devices

Details Parallel configuration of programmable devices Parallel configuration of programmable devices

2008-06-09

2009-11-24

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S039000, C326S040000

Reexamination Certificate

active

07622948

ABSTRACT:
A system for configuring a plurality of programmable devices may include an external memory, a master programmable device, and at least one slave programmable device. The programmable devices may have a parallel data bus connected in a daisy chain fashion. The programmable devices may further include a chip select signal that is also connected in a daisy chain. Special instructions embedded in the configuration bitstream, which may be stored in the external memory, are used by the programmable devices to control the configuration process.

REFERENCES:
patent: 5640106 (1997-06-01), Erickson et al.
patent: 5760607 (1998-06-01), Leeds et al.
patent: 5789938 (1998-08-01), Erickson et al.
patent: 5794033 (1998-08-01), Aldebert et al.
patent: 5923614 (1999-07-01), Erickson et al.
patent: 6044025 (2000-03-01), Lawman
patent: 6326806 (2001-12-01), Fallside et al.
patent: 6614259 (2003-09-01), Couts-Martin et al.
patent: 6625796 (2003-09-01), Rangasayee et al.
patent: 6714044 (2004-03-01), Rangan et al.
patent: 6766505 (2004-07-01), Rangan et al.
patent: 7088132 (2006-08-01), Tang et al.
patent: 7095247 (2006-08-01), Tang et al.
patent: 7265578 (2007-09-01), Tang et al.
patent: 7358762 (2008-04-01), Walstrum et al.
Altera Corporation, “Configuring multiple Cyclone FPGAs with a single Configuration Device”,Cyclone Device Handbook, Section VI., Jul. 2003, pp. 13-1thru 14-30 (88 pages), vol. 1, available from Altera Corporation, 2610 Orchard Parkway, San Jose, California 95134-2020.
Xilinx, Inc., DS123, v2.8,“Platform Flash In-System Programmable Configuration PROMS”, Dec. 29, 2005, pp. 1-47, , available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124.
Xilinx, Inc., DS099-2, v1.3, “Spartan-3 FPGA Family Functional Description”, Aug. 24, 2004, pp. 1-39, available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124.
U.S. Appl. No. 11/378,817, filed Mar. 17, 2006, Wennekamp, Wayne Edward; entitled Parallel Configuration Of Programmable Devices, Xilinx, Inc. 2100 Logic Drive, San Jose, CA 95124.
U.S. Appl. No. 60/778,002, filed Feb. 28, 2006, Wennekamp, Wayne Edward; entitled Parallel Configuration Of Programmable Devices, Xilinx, Inc. 2100 Logic Drive, San Jose, CA 95124.

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