Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Patent
1993-12-10
1999-11-16
Beausoliel, Jr., Robert W.
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
G06F 1100
Patent
active
059876220
ABSTRACT:
A parallel computer system comprising a plurality of processing elements and an input/output system interconnected by a communications network. The input/output system includes a plurality of input/output devices connected to the communications network for receiving messages from, and transmitting messages to, the processing elements over the communications network. The processing element during the storage operation generates a series of messages for transmission over the communications network to successive input/output devices. Each message includes a data item from one of a series of storage locations. The processing element generates for each stripe of a selected number of data items a check value for transmission in a message to another of the input/output devices. During a reconstruction operation, the processing element receives the data items and the check values from at least some of the input/output devices and performs a reconstruction operation in connection with each check value and a stripe of data values for which the check value was generated during the storage operation thereby to reconstruct data items stored in at least one other of the input/output devices.
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Lee Roger
Lo Verso Susan
Rowe Eric L.
Sharakan Eric
Beausoliel, Jr. Robert W.
Elmore Stephen C.
TM Patents, LP
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