Parallel compression test circuit of memory device

Details Parallel compression test circuit of memory device Parallel compression test circuit of memory device

2006-05-16

2006-05-16

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S230030, C365S189040

Reexamination Certificate

active

07046563

ABSTRACT:
A parallel compression test circuit of a memory device operates write drivers sequentially in a parallel compression test to disperse peak current and reduce noise. The circuit comprises a write driving control unit for generating a plurality of write driving control signals in response to a column operation pulse signal at the same timing in a normal mode, at a different timing in the parallel compression test mode.

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patent: 2001/0028583 (2001-10-01), Tsukude
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patent: 2000-322900 (2000-11-01), None

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