Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
1998-08-27
2001-02-20
De Cady, Albert (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
Reexamination Certificate
active
06192497
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to hard disk error correction code decoders, and more particularly to devices and methods for solving error locator polynomials.
2. Description of the Related Art
Modern computer systems generally include one or more hard disk drives to store large amount of data and programs. Hard disk drives typically store information in sequence by using magnetic technology. Like most recording technology, reading the sequential data bits from a hard disk often generates errors due to noise, manufacturing imperfections of the physical medium, dust, etc.
To detect and correct such errors, hard disk drives typically implement an error correction code (ECC) scheme in writing to and reading from hard disk drives. These hard disk drives generally include ECC circuitry that implement ECC schemes using well known codes such as Reed-Solomon codes to encode user data for reliable recovery of the original data through an ECC decoder. This helps to achieve a higher areal density.
Conventional ECC schemes compute ECC bytes for a given block of user data such as a data sector. The computed ECC bytes are appended to the block of user data sector and then recorded on a hard disk. When the entire sector is read, the ECC approach computes error locations and error patterns in the user data by decoding the ECC bytes.
Prior Art
FIG. 1
illustrates a block diagram of a conventional computer system
100
including a host computer
118
that receives data from a disk
102
in a hard disk drive. A motor
104
spins the disk
102
containing the data. A read/write head
106
attached to an actuator
108
searches for a track and sectors that contain the desired data. Upon finding the desired sectors, the read/write head
106
reads the data sequentially from the disk
102
. An amplifier
110
amplifies the data signals and transmits the amplified data signals to an analog-to-digital converter
112
.
The analog-to-digital converter
112
converts the amplified data signals into digital data bits and transmits the data bits to a deserializer
114
. The deserializer
114
receives the sequential data bits and converts the data into a series of blocks called sectors, each of which is typically 512 bytes of user data and ECC bytes appended to the user data bytes. The deserializer
114
sequentially transmits the sectors to an error detection and correction (EDAC) circuitry
116
, which detects errors in the received sector and, if correctable, corrects the detected errors using an ECC scheme. The EDAC circuitry
116
then transmits the error corrected user data to the host computer
118
.
The EDAC circuitry
116
typically employs a conventional Reed-Solomon code in its ECC scheme to encode user data for reliable recovery of the original data. Under the Reed-Solomon code ECC scheme, assuming &Lgr;(z) is an error locator polynomial that has its roots the inverses of the &ngr; error locators {&agr;
i
k
}, then the error locator polynomial &Lgr;(z) can be expressed as:
Λ
(
z
)
=
∏
l
=
1
υ
(
1
-
Z
α
i
l
)
=
Λ
υ
z
υ
+
Λ
υ
-
1
z
υ
-
1
+
…
+
Λ
1
z
+
Λ
0
(
2
)
Equation (2) can be used to evaluate the error locator polynomial &Lgr;(z) at all nonzero field elements, &agr;
0
to &agr;
2
b
−2
in a finite field, where b is the number of bits in a symbol (e.g., byte). For example, for a byte containing 8 bits, the field GF(2
8
) includes 255 field elements from &agr;
0
to &agr;
254
. The error locator polynomials and Galois fields are well known in the art and is described, for example, in Error Control Systems for Digital Communication and Storage, by Stephen B. Wicker, 1995, ISBN 0-13-200809-2, which is incorporated herein by reference.
Prior Art
FIG. 2
shows a more detailed block diagram of the EDAC circuitry
116
that utilizes the ECC scheme. The EDAC circuitry
116
receives a sector
200
of user data bytes of 512 bytes and additional ECC bytes in a sequential manner. At the front end of the EDAC circuitry
116
, a syndrome generator
202
receives the sector
200
and generates partial syndromes from the received sector data. Syndrome generators are well known in the art and are typically implemented as a linear feedback shift register circuit. The generated partial syndrome indicates whether an error is present in the received sector
200
. For example, a zero syndrome indicates that no error has been detected. On the other hand, a nonzero syndrome indicates that one or more errors has been detected in the received data.
The generated partial syndromes are then transmitted to an ECC decoder
204
, which includes error locator polynomial generator
206
, an error locator polynomial solver
208
, and an error pattern generator
210
. The error locator polynomial generator
206
receives the partial syndromes from the syndrome generator
202
and generates a set of coefficients (i.e., &Lgr;
i
s) for the received sector
200
. The generated set of coefficients defines an error locator polynomial. Using the coefficients defining the error locator polynomial, the error locator polynomial solver
208
sequentially computes the error locations (e.g., byte locations) in the received sector by determining the roots of the error locator polynomial and feeds the error locations to the error pattern generator
210
. The error pattern generator
210
computes error patterns in the received sector
200
using the error locations and partial syndromes. The EDAC circuitry
116
then uses the error locations and error patterns to correct the errors in the received sector.
The error locator polynomial solver
208
is typically implemented by means of a conventional Chien search technique to determine error locations, &agr;
i
s, from the coefficients of an error locator polynomial, &Lgr;(z). The Chien search technique is a systematic means of evaluating the error locator polynomial at all elements in a field GF(2
m
). Each coefficient &Lgr;
i
of the error locator polynomial, for i greater than 0, is repeatedly multiplied by &agr;
i
. Each set of the products is then summed and compared with 1. If the sum is equal to 1, then &agr;
i
is a root of the error locator polynomial, &Lgr;(z), and an error is indicated at the coordinate or location associated with &agr;
−i
=&agr;
n−i
, where the data bytes in a received sector are labeled (r
0
, r
1
, . . . , r
n−1
). Chien search techniques and circuits are well known in the art and are described, for example, in Error Control Systems for Digital Communication and Storage, Stephen B. Wicker, 1995, ISBN 0-13-200809-2, on pages 204-211, the disclosure of which is incorporated herein by reference.
Prior Art
FIG. 3
illustrates a conventional Chien search circuit
208
for finding a set of error locations by evaluating an error locator polynomial at all elements from &agr;
0
to &agr;
254
sequentially in a field GF(2
8
). In particular, the Chien search circuit
208
determines the roots to the error locator polynomial defined by a set of coefficients including &Lgr;
1
, &Lgr;
2
, &Lgr;
3
, &Lgr;
4
, &Lgr;
5
, and &Lgr;
6
(&Lgr;
1
to &Lgr;
6
hereinafter). The Chien search circuit
208
includes a set of storage elements
302
,
304
,
306
,
308
,
310
, and
312
(
302
to
312
hereinafter), which initially receive and store the set of coefficients, &Lgr;
1
to &Lgr;
6
, respectively.
Each of the storage elements
302
through
312
is associated with a constant GF multiplier, which is well known in the art. Specifically, the storage elements
302
to
312
are coupled to constant multipliers
318
,
320
,
322
,
324
,
326
, and
328
(
318
to
328
hereinafter), respectively, in a feedback configuration. The constant multipliers
318
to
328
, respectively, are operative to multiply constants &agr;
1
, &agr;
2
, &agr;
3
, &agr;
4
, &agr;
5
, and &agr;
6
, respectively, with the coefficients &Lgr;
1
, &Lgr;
2
, &Lgr;
3
, &Lg
Gill, III John T.
Yang Honda
Adaptec, Inc.
Cady Albert De
Chase Shelly A
Martine Penilla & Kim LLP
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