Parallel CCD memory chip and method of matching therewith

Details Parallel CCD memory chip and method of matching therewith Parallel CCD memory chip and method of matching therewith

1993-03-09

1995-01-31

LaRoche, Eugene R.

Static information storage and retrieval

Systems using particular element

Semiconductive

377 60, 377 62, 377 63, G11C 1928, H03K 2346

Patent

active

053863844

ABSTRACT:
A fully parallel CCD memory chip of N address lines which detects in just one clock cycle, a perfect match between an input pattern and any of a plurality of stored patterns and also detects in less than (N+1)-comparison cycles and still just one XOR operation, the best matching in case a perfect one does not exist. The chip disclosed herein has a fully parallel architecture in which an input word is compared to all stored words at one time. A preferred embodiment of the invention uses a four phase CCD, wherein each stored word occupies one row of the CCD and each such bit of each such word occupies two cells. Where perfect matches exist, only one comparison clock cycle is needed to compare the input word with all stored words and where there is no perfect match, the best match will be detected on a subsequent comparison pulse. Charge packets represent binary words generated by external pulses that are applied to the chip through data input lines and then are compared to the data applied to the address lines. The sensing is done directly on the cells in a non-destructive sensing process in parallel, rather than at the end of each row.

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patent: 4766332 (1988-08-01), Pelgrom et al.
patent: 4987558 (1991-01-01), Slob

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