Parallel caches operating in exclusive address ranges

Details Parallel caches operating in exclusive address ranges Parallel caches operating in exclusive address ranges

2011-06-28

2011-06-28

Thomas, Shane M (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711SE12017, C711S003000

Reexamination Certificate

active

07970998

ABSTRACT:
A cache memory of the present invention includes a second cache memory that is operated in parallel with a first cache memory, a judgment unit which, when a cache miss occurs in both of the first cache memory and the second cache memory, makes a true or false judgment relating to an attribute of data for which memory access resulted in the cache miss, and a controlling unit which stores memory data in the second cache memory when a judgment of true is made, and stores the memory data in the first cache memory when a judgment of false is made.

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