Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2001-06-27
2008-09-09
Vital, Pierre (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S150000, C711S168000, C711S210000
Reexamination Certificate
active
07424576
ABSTRACT:
Parallel cachelets are provided for a level of cache in a microprocessor. The cachelets may be independently addressable. The level of cache may accept multiple load requests in a single cycle and apply each to a respective cachelet. Depending upon the content stored in each cachelet, the cachelet may generate a hit/miss response to the respective load request. Load requests that hit their cachelets may be satisfied therefrom. Load requests that miss their cachelets may be referred to another level of cache.
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Limaye Deepak
Rakvic Ryan N.
Shen John P.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Rojas Midys
Vital Pierre
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