Parallel cachelets

Details Parallel cachelets Parallel cachelets

2007-05-08

2007-05-08

Kim, Hong (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S150000, C711S168000, C711S210000

Reexamination Certificate

active

11327454

ABSTRACT:
Parallel cachelets are provided for a level of cache in a microprocessor. The cachelets may be independently addressable. The level of cache may accept multiple load requests in a single cycle and apply each to a respective cachelet. Depending upon the content stored in each cachelet, the cachelet may generate a hit/miss response to the respective load request. Load requests that hit their cachelets may be satisfied therefrom. Load requests that miss their cachelets may be referred to another level of cache.

REFERENCES:
patent: 4905141 (1990-02-01), Brenza
patent: 5210842 (1993-05-01), Sood
patent: 5381533 (1995-01-01), Peleg et al.
patent: 5410668 (1995-04-01), Hilton
patent: 5432947 (1995-07-01), Doi
patent: 5495617 (1996-02-01), Yamada
patent: 5530932 (1996-06-01), Carmean et al.
patent: 5630146 (1997-05-01), Conary et al.
patent: 5632038 (1997-05-01), Fuller
patent: 5634131 (1997-05-01), Matter et al.
patent: 5666513 (1997-09-01), Whittaker
patent: 5666537 (1997-09-01), Debnath et al.
patent: 5752045 (1998-05-01), Chen
patent: 5781783 (1998-07-01), Gunther et al.
patent: 5796978 (1998-08-01), Yoshioka et al.
patent: 5809532 (1998-09-01), Eno et al.
patent: 5901322 (1999-05-01), Herbst et al.
patent: 5913223 (1999-06-01), Sheppard et al.
patent: 5931951 (1999-08-01), Ando
patent: 6041401 (2000-03-01), Ramsey et al.
patent: 6115793 (2000-09-01), Gruber et al.
patent: 6128704 (2000-10-01), Jun
patent: 6167510 (2000-12-01), Tran
patent: 6219796 (2001-04-01), Bartley
patent: 6307281 (2001-10-01), Houston
patent: 6327643 (2001-12-01), Egan
patent: 6349364 (2002-02-01), Kai et al.
patent: 6381671 (2002-04-01), Ayukawa et al.
patent: 6427188 (2002-07-01), Lyon et al.
patent: 6442667 (2002-08-01), Shiell et al.
patent: 6449694 (2002-09-01), Burgess, Jr. et al.
patent: 6528974 (2003-03-01), Mirov et al.
patent: 6549987 (2003-04-01), Rappoport et al.
patent: 6608476 (2003-08-01), Mirov et al.
patent: 2002/0129201 (2002-09-01), Maiyuran et al.
patent: WO 97/37307 (1997-10-01), None
Agarwal et al, “Column-Associative Caches: A Technique for Reducing the Miss Rate of Direct-Mapped Caches”, Proceedings, The 20thAnnual Intl Symposium on Computer Architecture, IEEE Computer Society, Technical Committee on Computer Architecture, Association for Computing Machinery SIGARCH, pp. 169-190, San Diego, California, May 16-19, 1993.
Alexander et al, “Distributed Prefetch-buffer/Cache Design for High Performance Memory Systems”, Proceedings, Second Intl Symposium on High-Performance Computer Architecture, IEEE Computer Society, Technical Committee on Computer Architecture, pp. 254-263, San Jose, California, Feb. 3-7, 1996.
Burger et al, “The SimpleScalar Tool Set, Version 2.0”,Computer Sciences Department Technical Report, No. 1342, The University of Wisconsin, Madison, Wisconsin, Jun. 1997.
Edmondson et al, “Internal Organization of the Alpha 21164, a 300-MHz 64-bit Quad-issue CMOS RISC Microprocessor”,Digital Technical Journal, vol. 7, No. 1, pp. 119-135, 1995.
Hill, Mark D., “A Case for Direct-Mapped Caches”,Computer, pp. 25-40, Dec. 1988.
Juan et al, “The Difference-bit Cache”, Proceedings, The 23rdAnnual Int'l Symposium on Computer Architecture, ACM SIGARCH, IEEE Computer Society, TCCA, pp. 114-120, Philadelphia, Pennsylvania, May 22-24, 1996.
Kessler et al, “Inexpensive Implementation of Set-Associativity”, Proceedings, The 16thAnnual Intl Symposium on Computer Architecture, IEEE Computer Society Press, pp. 131-139, 1989.
Rau et al, “Pseudo-Randomly Interleaved Memory”, Proceedings, The 18thAnnual Intl Symposium on Computer Architecture, Association for Computing Machinery, pp. 74-83, Toronto, Canada, May 27-30, 1991.
Rivers et al, “On Effective Data Supply for Multi-Issue Processors”, Proceedings, Intl Conference on Computer Design, VLSI in Computers and Processors, IEEE Computer Society Technical Committee on Design Automation, IEEE Circuits and Systems Society, pp. 519-528, Austin, Texas, Oct. 12-15, 1997.
Sánchez et al, “A Locality Sensitive Multi-Module Cache with Explicit Management”, Proceedings of the 1999 Intl Conference on Supercomputing, ICS '99, Rhodes, Greece.
Sohi et al, “High-Bandwidth Data Memory Systems for Superscalar Processors”, ASPLOS-IV Proceedings, Fourth Intl Conference on Architectural Support for Programming Languages and Operating Systems, pp. 53-62, Santa Clara, California, Apr. 8-11, 1991.
Wilson et al, “Increasing Cache Port Efficiency for Dynamic Superscalar Microprocessors”, Proceedings, The 23rdAnnual Intl Symposium on Computer Architecture, ACM SIGARCH, IEEE Computer Society, TCCA, pp. 147-157, Philadelphia, Pennsylvania, May 22-24, 1996.
Wilson et al, “Designing High Bandwidth On-Chip Caches”, The 24thAnnual Intl Symposium on Computer Architecture, Conference Proceedings, ACM, pp. 121-132, Denver, Colorado, Jun. 2-4, 1997.
Wilton et al, “An Enhanced Access and Cycle Time Model for On-Chip Caches”, Digital WRL Research Report 93/5, Palo Alto, California, Jul. 1994.
Albonesi, “Selective Cache Ways: On-Demand Cache Resource Allocation” pp. 248-259, IEEE, Nov. 1999.
Microsoft Computer Dictionary, Copyright 1999, Microsoft Press, Fourth Edition, p. 12.
Shanley, T.,Pentium® Pro Processor System Architecture, Chapter 5, pp. 61-118, Addison-Wesley Developers Press, 1997.
The Authoritative dictionary of IEEE Standards Terms, 2000, IEEE Press, Seventh Edition, p. 519.
Rivers et al, “On High-Bandwidth Data Cache Design for Multi-Issue Processors”, IEEE, Proceedings, Micro-30, Dec. 1-3, 1997, Research Triangle Park, North Carolina.
Neefs et al, A Technique for High Bandwidth and Deterministic Low Latency Load/Store Accesses to Multiple Cache Banks, 6th Int'l. Symposium on High-Performance Computer Architecture HPCA-6, IEEE, 1999, Los Alamitos, California.
Calder et al, “Predictive Sequential Associative Cache”, IEEE. Proceedings 2nd Int'l. Symposium on High-Performance Computer Architecture, Feb. 3-7, 1996, San Jose, California.
Cho et al, Decoupling Local Variable Accesses in a Wild-Issue Superscalar Processor, Proceedings of the 26th Annual Int'l. Symposium on Computer Architecture, May 1999.
Black et al, “The Block-Based Trace Cache”, Proceedings of The 26th Int'l. Symposium on Computer Architecture, pp. 196-207, May 2-4, 1999, Atlanta, Georgia.
Conte et al, “Optimization of Instruction Fetch Mechanisms for High Issue Rates”, Proceedings of the 22nd Annual Int'l Symposium on Computer Architecture, pp. 333-344, Jun. 22-24, 1995, Santa Margherita Ligure, Italy.
Dutta et al, “Control Flow Prediction with Tree-Like Subgraphs for Superscalar Processors”, Proceedings of The 28th Int'l. Symposium on Microarchitecture, pp. 258-263, Nov. 29-Dec. 1, 1995, Ann Arbor, Michigan.
Friendly et al, “Alternative Fetch and Issue Policies for the Trace Cache Fetch Mechanism”, Proceedings of The 30thAnnual IEEE/ACM Int'l Symposium on Microarchitecture, pp. 24-33, Dec. 1-3, 1997, Research Triangle Park, North Carolina.
Intrater et al, “Performance Evaluation of a Decoded Instruction Cache for Variable Instruction-Length Computers”, Proceedings of the 19thAnnual Int'l Symposium on Computer Architecture, pp. 106-113, May 19-21, 1992, Gold Coast, Australia.
Jacobson et al, “Path-Based Next Trace Prediction”, Proceedings of the 30thAnnual Int'l Int'l Symposium on Microarchitecture, pp. 14-23, Dec. 1-3, 1997, Research Triangle Park, North Carolina.
McFarling, Scott, “Combining Branch Predictors”, Jun. 1993, WRL Technical Note TN-36, Digital Western Research Laboratory, pp. i-25, Palo Alto, California.
Michaud et al, “Exploring Instruction-Fetch Bandwidth Requirement in Wide-Issue Superscalar Processors”, Proceedings of the 1999 Int'l Conference on Parallel Architectures and Compilation Techniques, pp. 2-10, Oct. 12-16, 1999, Newport Beach,

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