Parallel cache interleave accesses with address-sliced...

Details Parallel cache interleave accesses with address-sliced... Parallel cache interleave accesses with address-sliced...

2006-05-02

2006-05-02

Padmanabhan, Mano (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S129000, C711S140000, C711S157000

Reexamination Certificate

active

07039762

ABSTRACT:
A microprocessor, having interleaved cache and two parallel processing pipelines adapted to access all of the interleaved cache. The microprocessor comprising: a cache directory for each of the parallel processing pipelines wherein each said cache directory is split according to the interleaved cache and interleaving of the cache directory is independent of address bits used for cache interleaving.

REFERENCES:
patent: 5497478 (1996-03-01), Murata
patent: 5559986 (1996-09-01), Alpert et al.
patent: 5740402 (1998-04-01), Bratt et al.
patent: 5909694 (1999-06-01), Gregor et al.
patent: 6446157 (2002-09-01), McGehearty et al.
patent: 6848023 (2005-01-01), Teramoto

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