Parallel bus system capable of expanding peripheral devices

Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus expansion or extension

Reexamination Certificate

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Reexamination Certificate

active

06442636

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a parallel bus system, and more particularly to a parallel bus system capable of accommodating the addition of peripheral devices to a “System on Chip” or other similar system.
BACKGROUND OF THE INVENTION
A “System on Chip” is generally as shown in
FIG. 1
, in which a chip
1
includes a central processing unit
11
, a decoder
12
, and several peripheral devices
13
,
14
, and
15
. Since the interconnections CS
1
, CS
2
, CS
3
and the bus
10
are fixed, it is very difficult to add other peripheral devices is needed. If two such Chips are connected for expanding, not only are the interconnections very complicated, but also the software programming is very tedious.
Up to the present, some serial bus systems are capable of expanding peripheral devices, but the related instructions and data transmission are very slow due to the series-connection thereof.
OBJECTS OF THE INVENTION
It is therefore an object of the present invention to provide a parallel bus system capable of expanding peripheral devices, such that related peripheral devices can be designed to adapt to it very easily for expanding the system.
It is another object of the present invention to provide a parallel bus system such that the peripheral devices can also control the bus for data transmission when needed.
It is a further object of the present invention to provide a parallel bus system that can include two or more central processing units to control the bus by time-sharing.


REFERENCES:
patent: 5619659 (1997-04-01), Kikinis et al.
patent: 5694557 (1997-12-01), Yang
patent: 5964856 (1999-10-01), Wu et al.
patent: 6282598 (2001-08-01), Manabe

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