Parallel buffer/driver configuration between data sending termin

Details Parallel buffer/driver configuration between data sending termin Parallel buffer/driver configuration between data sending termin

1994-12-13

1996-03-12

Nelms, David C.

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

326 82, H03K 1716

Patent

active

054989760

ABSTRACT:
A buffer/driver is arranged in parallel between the data sending terminal and the data receiving terminal of a data transmission system. The SETUP time and HOLD time requirements of the data receiving terminal may be satisfied at the same time in accordance with the present invention. A low end, which has medium amount of time delay, buffer/driver may be used in this present invention to achieve a high performance of the data transmission which is usually possible in the past through the utilization of a high end buffer/driver, which has extremely small amount of time delay.

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