Parallel backplane physical layer interface with scalable data b

Details Parallel backplane physical layer interface with scalable data b Parallel backplane physical layer interface with scalable data b

1998-06-03

2000-08-08

Sheikh, Ayaz R.

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

710131, 709249, G06F 1300

Patent

active

061015679

ABSTRACT:
An interface between a parallel backplane bus of a physical layer of a communication device and a higher layer of the device is provided in a manner compatible with a serial bus architecture such as IEEE 1394. The interface includes a parallel backplane physical layer controller having multiple receive data lines for receiving data from the backplane bus, and multiple transmit data lines for transmitting data to the backplane bus. A link layer controller is coupled to the parallel backplane physical layer controller, and communicates with the parallel backplane physical layer controller over a data bus. The parallel backplane physical layer controller can provide an effective data bandwidth which is greater than its operating clock rate. The parallel backplane physical layer controller may also be operative to support communications with the backplane bus using a plurality of different backplane bus widths, such as a single data bit bus width, a two data bit bus width, a four data bit bus width and an eight data bit bus width. The throughput data bandwidth of the interface can therefore be scaled by selecting one of the data bus widths supported by the parallel backplane physical layer controller.

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1. Institute of Electrical and Electronics Engineers (IEEE) Standard 1394-1995, "High Performance Serial Bus," 1995, pp. 1 and 313-314.
2. TSB14C01 Data Sheet, "5-V IEEE 1394-1995 Backplane Transceiver/Arbiter," Texas Instruments Inc., Dallas Texas, 1996.

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