Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2011-01-11
2011-01-11
Rizk, Sam (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S758000, C714S755000
Reexamination Certificate
active
07870458
ABSTRACT:
A decoding system (100) is provided. The decoding system is comprised of two or more serial concatenated convolutional code (SCCC) decoders (1021-102N) operating in parallel. The SCCC decoders are configured to concurrently decode codeblocks which have been encoded using a convolutational code. The decoding system is also comprised of a single common address generator (108) and data store (114). The address generator is responsive to requests for data needed by two or more of the SCCC decoders for permutation and depermutation. The data store is comprised of two or more memory blocks (1161-116K). The SCCC decoders concurrently generate requests for two or more different data types. Selected ones of the different data types are exclusively stored in different ones of the memory blocks. Selected ones of the different data types are comprised of data which is requested at the same time by a particular one of the SCCC decoders.
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Cobb Matthew C.
Dyson Timothy F.
Laprade Maria
Fox Rothschild LLP
Harris Corporation
Rizk Sam
Sacco Robert J.
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