Computer graphics processing and selective visual display system – Computer graphic processing system – Plural graphics processors
Reexamination Certificate
2006-10-10
2006-10-10
Tung, Kee M. (Department: 2628)
Computer graphics processing and selective visual display system
Computer graphic processing system
Plural graphics processors
C345S422000
Reexamination Certificate
active
07119809
ABSTRACT:
A parallel architecture for determining pixels inside a graphics primitive is provided. The architecture is a pipeline structure having a predetermined number of sequential logic circuits connected in series followed by a predetermined number of parallel logic circuits arranged in a pyramid structure. Each sequential logic circuit uses arithmetic edge functions corresponding to edges of a graphics primitive to determine whether a polygonal portion of a raster image is inside the graphics primitive. If the polygonal portion is at least partly inside the graphics primitive, the sequential logic circuit divides the polygonal portion into a predetermined number of subportions and computes descriptors (e.g., vertices and translated edge functions) for each subportion sequentially. Descriptors are then transferred sequentially to the next stage. Each parallel logic circuit performs the same functions as that of a sequential logic circuit except that a parallel logic circuit computes descriptors of the subportions in parallel and transfers them to the next stage in parallel.
REFERENCES:
patent: 5287438 (1994-02-01), Kelleher
patent: 5392392 (1995-02-01), Fischer et al.
patent: 5416893 (1995-05-01), Herrell et al.
patent: 5579455 (1996-11-01), Greene et al.
patent: 5600763 (1997-02-01), Greene et al.
patent: 5963210 (1999-10-01), Lewis et al.
patent: 5995439 (1999-11-01), Watanabe et al.
patent: 6057855 (2000-05-01), Barkans
patent: 6236404 (2001-05-01), Iimura et al.
patent: 6329996 (2001-12-01), Bowen et al.
patent: 6359623 (2002-03-01), Larson
patent: 6407736 (2002-06-01), Regan
patent: 6480205 (2002-11-01), Greene et al.
patent: RE38078 (2003-04-01), Duluk, Jr.
M. D. McCool, “Incremental and Hierarchical Hilbert Order Edge Equation Polygon Rasterization”, Proceedings of the ACM SIGGRAPH/Eurographics workshop on on Graphics hardware, Aug. 2001, Los Angeles, CA, pp. 65-72.
Ned Greene, “Hierarchical polygon tiling with coverage masks”, Proceedings of the 23rd annual conference on Computer graphics and interactive techniques, p. 65-74, Aug. 1996.
H. Fuchs , et al., “Fast spheres, shadows, textures, transparencies, and imgage enhancements in pixel-planes”, Proceedings of the 12th annual conference on Computer graphics and interactive techniques, pp. 111-120, Jul. 1985.
H. Fuchs, et. al., “Pixel-planes 5: a heterogeneous multiprocessor graphics system using processor-enhanced memories”, ACM SIGGRAPH Computer Graphics , Computer Graphics, pp. 79-88, Jul. 1989, vol. 23, No. 3.
U.S. Appl. No. 09/858,306, Daniel H. McCabe, Graphics Primitive Decomposition Using Edge Functions and Recursive Tile Subdivision, filed May 15, 2001.
M. Olano, T. Greer, “Triangle Scan Conversion Using 2D Homogeneous Coordinates,” Proceedings of the 1997 SIGGRAPH/Eurographics Workshop on Graphics Hardware, Aug. 1997, pp. 89-95.
Carr & Ferrell LLP
S3 Graphics Co., Ltd.
Wang Jin-Cheng
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