Parallel adder-based DCT/IDCT design using cyclic convolution

Details Parallel adder-based DCT/IDCT design using cyclic convolution Parallel adder-based DCT/IDCT design using cyclic convolution

2006-10-03

2006-10-03

Mai, Tan V. (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S402000

Reexamination Certificate

active

07117236

ABSTRACT:
The present invention provides a device and method for applying 1-D and 2-D DCT and IDCT transforms to sets of input data, typically 8×8 or 16×16 matricies of coefficients. In one embodiment, the present invention provides input lines, logic to pre-add input values and generate operands and one or more adder networks that effectively carry out the multiplication operations required to apply a DCT/IDCT transform. The device may apply a 1-D transform twice to accomplish a 2-D transform. Alternatively, the present invention may either include successive stages of logic for the second 1-D transform or it may send data transformed once back through the same logic to pre-add and adder networks for the second 1-D transform. Calculations may be carried out after Booth encoding of operands. The processing may be split between producing vp, a vector of sums of output values, and producing vn, a vector of differences of output values, which vectors may be recombined to produce an output vector v.

REFERENCES:
patent: 3878985 (1975-04-01), Ghest et al.
patent: 4156920 (1979-05-01), Winograd
patent: 4646256 (1987-02-01), Bracewell
patent: 4797847 (1989-01-01), Duhamel
patent: 5231601 (1993-07-01), Stearns
patent: 5677863 (1997-10-01), Naffziger
patent: 5805482 (1998-09-01), Phillips
patent: 5859788 (1999-01-01), Hou
patent: 5867414 (1999-02-01), Kao
patent: 5867601 (1999-02-01), Phillips
patent: 5889690 (1999-03-01), Arakawa
patent: 5889692 (1999-03-01), Wolrich et al.
patent: 5892698 (1999-04-01), Naffziger
patent: 6223195 (2001-04-01), Tonomura
David Akopian et al., “Pipeline Processor for Fast Architecture Oriented Regular DCT-IDCT Algorithm,” Signal Processing Laboratory, Tampere University of Technology, Finland, pp. 1319-1322.
“Compression Technology: an MPEG Overview,” downloaded from: http://www.c-cube.com/technology/mpeg.html pp. 1-11.
“The Implementation of the 2D-IDCT”, downloaded from: http://rnvs.infomatik.tu-chemnitz.de/˜ja/MPEG/HTML/IDCT.html pp. 1-12.
Romesh M. Jessani et al., “Comparison of Single- and Dual-Pass Multiply-Add Fused Floating-Point Units,” IEEE Transactions on Computers, vol. 47, No. 9, Sep. 1999, pp. 927-937.
Yutai Ma, “A Simplified Architecture for Module (2n+1) Multiplication,” IEEE Transactions on Computers, vol. 47, No. 3, Mar. 1998, pp. 333-337.
Vojin G. Oklobdzija et al., “A Method for Speed Optimized Partial Product Reduction and Generation of Fast Parallel Multipliers Using an Algorithmic Approach,” IEEE Transactions on Computers, vol. 45, No. 3, Mar. 1996, pp. 294-306.
Ioannis Pitas et al, “Multidimensional Cyclic Convolution Algorithms with Minimal Multiplicative Complexity,” IEEE Transactions on Acoustics, Speech and Signal Processing, vol. ASSP-35, No. 3, Mar. 1987, pp. 384-390.
Jacques Prado et al., “A Polynomial-Transform Based Computation of the 2-D DCT with Minimum Mulitplicative Complexity,” Telecom-Paris Department Signal, France, pp. 1-5.
K. R. Rao et al, Discrete Cosine Transform, Academic Press, Inc., Harcourt Brace Jovanovich, pp. 110-114.
Ross Smith et al., “An Asynchronous 2-D Discrete Cosine Transform Chip,” Theseus Logic, Inc., St. Paul, Minnesota, USA, pp. 1-10.
Marvi Teixeira et al., “A Class of Fast Cyclic Convolution Algorithms Based on Block Pseudocirculants,” IEEE Signal Processing Letters, vol. 2, No. 5, May 1995, pp. 92-94.
Roger Woods et al., “Applying an XC6200 to Real-Time Image Processing,” IEEE Design & Test of Computers, Jan.-Mar. 1998, pp. 30-38.

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