Parallel access micro-TLB to speed up address translation

Details Parallel access micro-TLB to speed up address translation Parallel access micro-TLB to speed up address translation

1996-12-24

1998-11-10

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Address formation

Address mapping

711202, 711205, 711204, 711145, 711151, 711152, 711158, 711163, G06F 1210, G06F 922

Patent

active

058359621

ABSTRACT:
A memory management unit (MMU) includes a translation lookaside buffer capable of simultaneously servicing three requests supplied to the MMU by an instruction cache and two data caches, respectively. Also, an arbiter selects one of several pending requests from sources of different priorities for immediate processing by the MMU, using a process which avoids undue delay in servicing requests from sources of lower priority.

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patent: 5388215 (1995-02-01), Baker et al.
patent: 5426750 (1995-06-01), Becker et al.
patent: 5428757 (1995-06-01), Sutton

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