Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Making plural separate devices
Reexamination Certificate
1998-12-03
2003-05-27
Whitehead, Jr., Carl (Department: 2822)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Making plural separate devices
C438S108000, C257S685000
Reexamination Certificate
active
06569710
ABSTRACT:
TECHNICAL FIELD
The present invention generally relates to interconnection structures for joining an integrated semiconductor device or “chip” to a carrier substrate of organic nature. More particularly, the present invention concerns an interconnection structure separable into a plurality of individual chip modules, and a method of making the interconnection structure and a high volume of the individual modules. The present invention is especially concerned with “controlled collapse chip connection” or “C4” structures that employ solder-bump interconnections, which is also referred to as “face down” or “flip-chip” bonding.
BACKGROUND ART
Controlled collapse chip connection (C4) or flip-chip technology has been successfully used for over twenty-five years for interconnecting high I/O (input/output) count and area array solder bumps on silicon chips mounted to base ceramic chip carriers, for example alumina carriers. The solder bump, typically a 95 Pb/5 Sn alloy, provides the means of chip attachment to the ceramic chip carrier for subsequent usage and testing. For example, see U.S. Pat. Nos. 3,401,126 and 3,429,040 to Miller and assigned to the assignee of the present disclosure, for a further discussion of the controlled collapse chip connection (C4) technique of face down bonding of semiconductor ships to a carrier. Typically, a malleable pad of metallic solder is formed on the semiconductor device contact site and solder joinable sites are formed on the chip carrier.
The solder joinable sites on the carrier are surrounded by non-solderable barriers so that when the solder on the semiconductor device contact sites melts, surface tension of the molten solder prevents collapse of the joints and thus holds the semiconductor device (chip) suspended above the carrier. With the development of the integrated circuit semiconductor device technology, the size of individual active and passive elements have become very small, and the number of elements in the device has increased dramatically. This results in significantly larger chip sizes with larger numbers of I/O terminals. This trend will continue and will place increasingly higher demands on device forming technology. An advantage of solder joining a device to a substrate is that the I/O terminals can be distributed over substantially the entire surface of the semiconductor device. This allows efficient use of the entire surface, which is more commonly known as area bonding.
Usually the integrated circuit semiconductor chips are mounted on supporting substrates made of materials with coefficients of expansion that differ from the coefficient of expansion of the material of the semiconductor chip, e.g., silicon. Normally, the chip is formed of monocytstalline silicon with a coefficient of expansion of 2.6×10
−6
per ° C. and the substrate is formed of a ceramic material, typically alumina with a coefficient of expansion of 6.8×10
−6
per ° C. In operation, the active and passive elements of the integrated semiconductor chip inevitably generate heat resulting in temperature fluctuations in both the chips and the supporting substrate since the heat is conducted through the solder bonds. The chips and the substrate thus expand and contract in different amounts with temperature fluctuations, due to the different coefficients of expansion. This imposes stresses on the relatively rigid solder terminals.
The stress on the solder bonds during operation is directly proportional to (1) the magnitude of the temperature fluctuations, (2) the distance of an individual bond from the neutral or central point (DNP), and (3) the difference in the coefficients of expansion of the material of the semiconductor device and the substrate, and is inversely proportional to the height of the solder bond, that is the spacing between the device and the supporting substrate. The seriousness of the situation is further compounded by the fact that as the solder terminals become smaller in diameter in order to accommodate the need for greater density, the overall height decreases.
The disclosure of an improved solder interconnection structure with increased fatigue life can be found in U.S. Pat. No. 4,604,644 to Beckham et al., and assigned to the assignee of the present disclosure, the entire contents of which are incorporated herein by reference. In particular, U.S. Pat. No. 4,604,644 discloses a structure for electrically joining a semiconductor device to a support substrate that has a plurality of solder connections where each solder connection is joined to a solder wettable pad on the support substrate. A dielectric organic material is disposed between the peripheral area of the device and the facing area of the substrate, and this material surrounds and encapsulates at least one outer row and column of solder connections but leaves the solder connections in the central area of the device free of the dielectric organic material. The dielectric material is typically applied by first mixing it with a suitable solvent and then dispensing it along the periphery of the device where it can be drawn in between the device and substrate by capillary action.
Encapsulants that exhibit, among other things, improved fatigue life of C4 solder connections are disclosed in U.S. Pat. No. 4,999,699 to Christie et al. and assigned to the assignee of the present disclosure, the entire contents of which are incorporated herein by reference. In particular, U.S. Pat. No. 4,999,699 discloses a curable composition containing a binder which is a cycloaliphatic polyepoxide and/or a cyanate ester or prepolymer thereof and a filler. U.S. Pat. No. 5,121,190 to Hsiao et al. and assigned to the assignee of the present disclosure, the entire contents of which are incorporated herein by reference, discloses providing C4 solder connections for an integrated semiconductor device on an organic substrate. The compositions disclosed therein are curable compositions containing a thermosetting binding and filler. The binder employed has viscosity at normal room temperatures (25° C.) of no greater than about 1,000 centipoise. Suitable binders disclosed therein include polyepoxides, cyanate esters and prepolymers thereof.
In addition, U.S. Pat. No. 5,536,765 to Papathomas and assigned to the assignee of the present disclosure, the entire contents of which are incorporated herein by reference, discloses compositions that exhibit excellent wetting and coverage of the C4 connections as well as the pin heads under the device that are present. In fact, these compositions make it possible to achieve complete coverage beneath the chip. These compositions, which include a triazine polymer that is a reaction product of (a) monocyanate and (b) dicyanate and/or a prepolymer thereof, are of relatively low viscosity prior to curing and thereby exhibit even and adequate flow under the semiconductor device. The solder interconnection for forming connections between an integrated semiconductor device and a carrier substrate includes a plurality of solder connections that extend from the carrier substrate to electrodes on the semiconductor device to form a gap between the carrier substrate and the semiconductor device. The gap is filled with a composition obtained from curing the disclosed composition.
The techniques described above enable chips to be attached directly on the surface of a board thereby eliminating an intermediate chip carrier. Although these techniques have been quite successful, there still remains room for improvement, especially with respect to the handling and rate of producing modules with organic base panels, such as those made of Teflon. Organic based modules are very prone to handling damage when assembled individually in accordance with past practices. Individual assembly is also costly per module because of the amount of handling and manipulation required to assemble each small module element one at a time, resulting in low yields of the assembled modules.
SUMMARY OF INVENTION
The present invention overcomes the foregoing problems of the prior art in that it provi
Brophy Jamie L.
Connolly Bove & Lodge & Hutz LLP
Fraley, Esquire Lawrence R.
International Business Machines - Corporation
Jr. Carl Whitehead
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