Paging receiver employing memory banking system

Details Paging receiver employing memory banking system Paging receiver employing memory banking system

1996-04-25

1998-09-01

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

For multiple memory modules

711 1, 711 2, 711 3, G06F 1206

Patent

active

058025430

ABSTRACT:
A paging receiver includes a receiver, a decoder 303, a central processing unit 102, a ROM 104 in which programs to be executed by the CPU and data are stored in a plurality of bank modes, a RAM 105, and a demodulated data outputting apparatus. The decoder includes a bank mode switching register 601 that is used to select a plurality of bank modes. The register stores an initial hardware value and a bank switch value that is used to select one of the plurality of bank modes upon initialization by software, and one of the plurality of bank modes is selected in accordance with the initial hardware value and the bank switch value by the software. When the capacity of the ROM is limited, the capacity of the ROM can be assured sufficiently only by selecting one of the bank modes, and software designing can proceed only after some change of design.

REFERENCES:
patent: 5249220 (1993-09-01), Moskowitz et al.
patent: 5412719 (1995-05-01), Hamamoto et al.
patent: 5426424 (1995-06-01), Vanden Heuvel et al.

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