Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
1998-04-17
2002-05-21
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S148000, C711S152000, C711S163000
Reexamination Certificate
active
06393530
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention pertains in general to a multiple processor system and, more particularly, to an interface between a system bus and a multiple processor system for handling interrupts therebetween.
BACKGROUND OF THE INVENTION
In order to increase the processing capability of any system, multiple processor arrays have been utilized. Typically, these multiple processor arrays are comprised of independent central processing units (CPUs) which are disposed in an array with each having a local bus with local peripheral units disposed thereabout. The local buses of each of the CPUs is then interfaced with a global bus. In turn, the global bus is interfaced with a system bus. One type of system bus is a VME bus.
When handling data flow between the system bus and each of the CPUs in the array of processors, traffic must be routed over the global bus. In order for information to be transmitted either from the processors to the system bus or from the system bus to the processors, there must be some type of arbitration. Typically, a bus request is sent out to the global bus control system and then the bus request granted to that requesting device. Data can then be transmitted over the bus in the appropriate manner. This is a conventional operation. However, the global bus becomes the limiting factor in transfer of data between processors and the system bus, and even between adjacent processors on the global bus. This is due to the fact that only one device can occupy the global bus at a given time.
One type of CPU that has been used widely is a Digital Signal Processor (DSP). These processors execute instructions at a very high rate but, unfortunately, like most processors, the architecture of the processor will determine the limitations of that processor with respect to communicating with the global bus, communicating with other processors and handling interrupts. Typically, most DSPs are designed for single chip use and must be provided with another layer of infrastructure in order to be incorporated into an array of microprocessors.
One difficulty in dealing with a multiple processor array is that of handling interrupts between the System Bus and the array of processors. This is due to the fact that a device on the System Bus side of the global bus sends out an interrupt in a normal matter which must then be transmitted to one or more of the processors in the array to be serviced. This requires the global bus to be occupied for the interrupt period in order for anyone of the processors to, first, recognize the interrupt and, second, to then service the interrupt. This is difficult when dealing with multiple processors in that some scheme must be developed in order to define which of the processors is to service the interrupt. This can be difficult if an interrupt is to be serviced by more than one processor.
SUMMARY OF THE INVENTION
The present invention disclosed and claimed herein comprises a paging system for a multi-processor system. This system includes a system address and system resources addressable within the system address space. A plurality of processing nodes are provided, each of the processing nodes having a processor within a defined addressable local memory space and local resources addressable by the processor in the local memory space. An interface is provided for each of the processing nodes for interfacing with the system. The nodes also include a paging device for paging a portion of the local address space to the system address space through the system interface. The unpaged portion of the local address space is reserved for the local resources and not addressable from the system. The paging device is operable to generate an address in the system address space.
In another aspect of the present invention, the paging device includes a paging register for containing the upper address bits of the address in the system address space and the address in the paged portion of the local address space comprising the lower address bits of the address in the system address. A multiplexer is provided for selecting the output of one of the paging registers for transfer through the interface to the system. An arbiter system is provided for selecting the output of one of the paging registers for transmission through the interface to the system in accordance with a predetermined arbitration scheme.
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Bartlett James R.
Greim Michael C.
Howison, Chauza, Thoma, Handley & Arnott, L.L.P.
Intelect communications, Inc.
Kim Matthew
Vital Pierre M
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