Paging cache optimization for virtual machine

Details Paging cache optimization for virtual machine Paging cache optimization for virtual machine

2009-09-15

2010-12-21

Bragdon, Reginald G (Department: 2189)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C711S208000, C711S006000, C711SE12059

Reexamination Certificate

active

07856542

ABSTRACT:
A system, method and computer program product for virtualizing a processor include a virtualization system running on a computer system and controlling memory paging through hardware support for maintaining real paging structures. A Virtual Machine (VM) is running guest code and has at least one set of guest paging structures that correspond to guest physical pages in guest virtualized linear address space. At least some of the guest paging structures are mapped to the real paging structures. For each guest physical page that is mapped to the real paging structures, paging means for handling a connection structure between the guest physical page and a real physical address of the guest physical page. A cache of connection structures represents cached paths to the real paging structures. Each path is described by guest paging structure descriptors and by tie descriptors. Each path includes a plurality of nodes connected by the tie descriptors. Each guest paging structure descriptor is in a node of at least one path. Each guest paging structure either points to other guest paging structures or to guest physical pages. Each guest paging structure descriptor represents guest paging structure information for mapping guest physical pages to the real paging structures.

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