Paged memory data processing system with overlaid memory control

Details Paged memory data processing system with overlaid memory control Paged memory data processing system with overlaid memory control

1998-01-20

2000-05-02

Cabeca, John W.

Electrical computers and digital processing systems: memory

Address formation

Address mapping

711209, 711206, 711203, 711103, G06F 1208, G06F 1210, G06F 1212, G06F 1200, G06F 1300

Patent

active

060584637

ABSTRACT:
A data processing system has a CPU (12) that accesses memory (16-18) through a memory management interface (14). The memory management interface (14) supports paging of modules of nonvolatile memory (16) into a defined paged memory area in the memory map. Memory control registers (80-87) to control programming and erasing of the modules of nonvolatile memory are simultaneously mapped into the memory map at a defined memory register area, wherein a page (90-97) of nonvolatile memory and its associated memory control registers (80-87) are selected and mapped into their respective defined areas in the memory map based on a single page select register (44).

REFERENCES:
patent: 4511964 (1985-04-01), Georg et al.
patent: 5095420 (1992-03-01), Eilert et al.
patent: 5394537 (1995-02-01), Courts et al.
patent: 5603011 (1997-02-01), Piazza
"MC68HC912B32 Technical Summary," Motorola Semiconductor Technical Data, Rev. 1; pp. 1-8, 20-31, 37-51; 1997.

Affiliated with

Also associated with

Rating

Paged memory data processing system with overlaid memory control does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Paged memory data processing system with overlaid memory control, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Paged memory data processing system with overlaid memory control will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1602429