Paged memory architecture for a single chip multi-processor with

Details Paged memory architecture for a single chip multi-processor with Paged memory architecture for a single chip multi-processor with

1996-09-30

1999-03-30

Pan, Daniel H.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711119, 711123, 711130, 711147, 711148, 711153, G06F 1312, G06F 1316

Patent

active

058900136

ABSTRACT:
A multiprocessor data processing system includes a private data bus and a private program bus coupled to each of the processors. Coupled between the private data buses is a plurality of memory banks, each of which can be dynamically switched between the processors to move blocks of data without physically transferring the data from one bank to another. Likewise, a plurality of memory banks is coupled between the program buses. These memory banks are loaded with pages of program instructions from external memory over a shared bus. Any one of the pages can be coupled to either of the processors on its respective private program bus. When the pages are coupled to the shared bus, they appear as a contiguous address space. When a page is coupled to one of the private program buses, the addressing mode is changed so that the page is mapped to a common address space. This permits the program code to be loaded into any available page, and the processors can execute the code regardless of where it has been loaded, thereby permitting easy relocatability.

REFERENCES:
patent: 4487873 (1984-12-01), Price et al.
patent: 5010476 (1991-04-01), Davis
patent: 5539896 (1996-07-01), Lisle
patent: 5611075 (1997-03-01), Garde
patent: 5630153 (1997-05-01), Intrater et al.
patent: 5685005 (1997-11-01), Garde et al.
patent: 5696913 (1997-12-01), Gove et al.
patent: 5768824 (1998-06-01), Ghosh
Doyle, Casey D.ed.. "Computer Dictionary: Second Edition." Redmond, WA: Microsoft Press, 1993 ISBN 1-55615-597-2, 1993.

Affiliated with

Also associated with

Rating

Paged memory architecture for a single chip multi-processor with does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Paged memory architecture for a single chip multi-processor with, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Paged memory architecture for a single chip multi-processor with will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1224129