Page stream sorter for DRAM systems

Details Page stream sorter for DRAM systems Page stream sorter for DRAM systems

2008-05-20

2008-05-20

Peugh, Brian R. (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C711S105000

Reexamination Certificate

active

10969683

ABSTRACT:
Circuits, methods, and apparatus for reordering memory access requests in a manner that reduces the number of page misses and thus increases effective memory bandwidth. An exemplary embodiment of the present invention uses an exposed FIFO structure. This FIFO is an n-stage bubble compressing FIFO that preserves the order of requests but allows bypassing to avoid page misses and their resulting delays. A specific embodiment exploits DRAM page locality by maintaining a set of history registers that track the last bank and row usage. Embodiments of the present invention may limit the number of times a request may be bypassed by incrementing an associated bypass counter each time the request is bypassed. Further, to avoid continuous page misses that may occur if requests alternate between two rows, a hold-off counter may be implemented.

REFERENCES:
patent: 5787482 (1998-07-01), Chen et al.
patent: 2004/0123055 (2004-06-01), Solomon et al.
Hwang, et al., “An X86 Load/store Unit with Aggressive Scheduling of Load/store Operations”, © 1998, p. 1-8.

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