Page mode editable real time read transfer

Details Page mode editable real time read transfer Page mode editable real time read transfer

1995-07-05

1997-03-18

Nelms, David C.

Static information storage and retrieval

Addressing

Multiple port access

36523009, 3652385, G11C 800

Patent

active

056129220

ABSTRACT:
An integrated memory circuit is presented for real time read transfers of data. The integrated memory circuit includes a dynamic random access memory (DRAM) and a serial memory. The integrated memory circuit can be used to randomly access data locations in a row of the DRAM and then transfer the entire row to the serial memory. These two functions can be performed in one memory row access cycle to eliminate time consuming pre-charge operations. The random access operations can include both reading from, and writing to the DRAM. Newly written data can be transferred to the serial memory for external communication.

REFERENCES:
patent: 5179372 (1993-01-01), West et al.
patent: 5208775 (1993-05-01), Lee
patent: 5235545 (1993-08-01), McLaury
patent: 5265050 (1993-11-01), McLaury
patent: 5282177 (1994-01-01), McLaury
patent: 5287324 (1994-02-01), Nagashima
patent: 5311478 (1994-05-01), Zagar et al.
patent: 5319603 (1994-06-01), Watanabe et al.
patent: 5325502 (1994-06-01), McLaury
patent: 5369622 (1994-11-01), McLaury

Affiliated with

Also associated with

Rating

Page mode editable real time read transfer does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Page mode editable real time read transfer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Page mode editable real time read transfer will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1711143