Page mode access for non-volatile memory arrays

Details Page mode access for non-volatile memory arrays Page mode access for non-volatile memory arrays

2011-07-19

2011-07-19

Le, Thong Q (Department: 2827)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S189040, C365S189150, C365S189160, C365S196000, C365S207000

Reexamination Certificate

active

07983104

ABSTRACT:
An array of non-volatile memory cells arranged in logical columns and logical rows, and associated circuitry to enable reading or writing one or more memory cells on a row in parallel. In some embodiments, the array of memory cells may include a phase change material. In some embodiments, the circuitry may include a write driver, a read driver, a sense amplifier, and circuitry to isolate the memory cells from the sense amplifier with extended refresh.

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patent: 2005/0169095 (2005-08-01), Bedeschi et al.

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