Page handling efficiency in a multithreaded processor

Details Page handling efficiency in a multithreaded processor Page handling efficiency in a multithreaded processor

2006-06-27

2006-06-27

Thai, Tuan V. (Department: 2186)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C711S154000, C711S206000

Reexamination Certificate

active

07069414

ABSTRACT:
In a multithreaded processor, the efficiency of instruction processing may be improved by suspending an executing thread during the translation of a virtual memory address to a physical memory address when the address translation data must be retrieved from storage external to the processor. The suspension of an executing thread allows an address translation to be performed for an instruction in another thread while the address translation data needed for the first thread is retrieved.

REFERENCES:
patent: 5671444 (1997-09-01), Akkary et al.
patent: 5778407 (1998-07-01), Glew et al.
patent: 5781790 (1998-07-01), Abramson et al.

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