Page handling efficiency in a multithreaded processor

Details Page handling efficiency in a multithreaded processor Page handling efficiency in a multithreaded processor

2002-06-24

2004-10-26

Thai, Tuan V. (Department: 2186)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C711S206000, C711S125000, C711S123000

Reexamination Certificate

active

06810472

ABSTRACT:

BACKGROUND
The following description relates to improving page handling performance in a multithreaded processor.
For a processor to execute an instruction, the instruction and data needed by the instruction typically are stored in the processor memory before the instruction is executed. This may require the translation of a virtual memory address used by an instruction to a physical memory address describing a storage location for the needed instruction or the data. The region of memory storing the instruction or data may be loaded into processor memory from storage (fetched) using the physical memory address. A processor may manage memory by organizing memory space into fixed-length portions (pages) that can be moved into, and out of, processor memory. The process of translating the virtual memory address and retrieving pages from storage may be referred to as page handling.
A processor may be capable of managing the execution of more than one thread (e.g., a set of independently executing instructions that are part of a processing task) at a time. It is advantageous for a processor to be able to execute instructions in a thread quickly.


REFERENCES:
patent: 5671444 (1997-09-01), Akkary et al.
patent: 5778407 (1998-07-01), Glew et al.
patent: 5781790 (1998-07-01), Abramson et al.

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