Page buffer and non-volatile memory device including the same

Details Page buffer and non-volatile memory device including the same Page buffer and non-volatile memory device including the same

2008-06-24

2008-06-24

Nguyen, Viet Q (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S205000, C365S185200, C365S189090, C365S189050

Reexamination Certificate

active

07391649

ABSTRACT:
In one aspect, a non-volatile memory device includes a non-volatile memory cell array and a page buffer. The page buffer includes a sense node selectively connected to a bit line of the memory cell array, a main latch circuit including first and second main latch nodes, where the first main latch node is selectively connected to the sense node, and a latch input node selectively connected to the first and second main latch nodes. The page buffer further includes a cache latch circuit including first and second cache latch nodes, a switching circuit which selectively connects the second cache latch node to the latch input node, and a shared sense circuit connected between to the latch input node and a reference potential. The shared sense circuit selectively connects the latch input node to the reference potential in response to a voltage of the sense node and a voltage of the first cache latch node.

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