Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2000-03-03
2003-01-21
Yoo, Do Hyun (Department: 2187)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S207000, C711S208000, C711S220000, C714S045000, C365S189070
Reexamination Certificate
active
06510507
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The technical field of this invention is complex integrated circuits including embedded digital processor cores and more particularly in the method of making address comparisons much more efficient.
BACKGROUND OF THE INVENTION
Programmable digital processors such as microprocessors and digital signal processors have become very complex machines. Testing these programmable digital processors has also become complex task. It is now common for semiconductor manufactures to build single integrated circuit programmable digital processors with millions of transistors. The current trend is to devote many of these transistors to on-chip cache memories. Even so, the number of logic circuits and their complex relationships makes testing such integrated circuits an increasingly difficult task.
A trend in electronics makes this testing problem more difficult. Single integrated circuit programmable digital processors are becoming more and more of the electronics of many end products. A single integrated circuit used in this way typically includes a programmable digital processor, read only memory storing the base program, read/write memory for operation and a set of peripherals selected for the particular product. This trend is known as system level integration. In the ultimate system level integration, all the electronics are embodied in a single integrated circuit. This level of integration is now achieved in electronic calculators. Many electronic calculators consist of a single integrated circuit, a keyboard, a display, the battery or solar panel power source and a plastic case. Such integration provides less “visibility” into the operation of the programmable digital signal processor. Because the address and data busses of the digital processor are no longer brought out the device pins, as was done in the past, it is more difficult to determine the behavior of the embedded processor from external connections.
Another trend in electronics makes this testing problem more difficult. Many new product applications require differing types of processing. Often control processes and user interface processes are better handled with a different programmable digital processor than digital signal processes. An example is wireless telephones. Many coding/decoding and filtering tasks are best handled by a digital signal processor (DSP). Other tasks such as dialing, controlling user inputs and outputs are best handled by microprocessors such as a RISC (Reduced Instruction Set Computer) processor. There is a trend for a system integrated circuit to include both a RISC processor and a DSP. These two processors will typically operate independently and employ differing instruction set architectures. Thus there may be more than one programmable digital processor on a single integrated circuit, each having limited visibility via the device pins.
Another problem is product emulation when employing these programmable digital processors. Product development and debugging is best handled with an emulation circuit closely corresponding to the actual integrated circuit to be employed in the final product. In circuit emulation (ICE) is in response to this need. An integrated circuit with ICE includes auxiliary circuit not needed in the operating product included solely to enhance emulation visibility. In the typical system level integration circuit, these emulation circuits use only a very small fraction of the number of transistors employed in operating circuits. Thus it is feasible to include ICE circuits in all integrated circuits manufactured. Since every integrated circuit can be used for emulation, inventory and manufacturing need not differ between a normal product and an emulation enhanced product.
Real-time trace and debug/analysis systems for embedded systems need to provide the user With means of triggering on selective events, such as the CPU accessing particular memory locations. This can be done with a single bus monitor, which compares the address on the bus to a reference address. If it matches, then the event occurs. This approach is typically expanded through the use of multiple point comparators used in parallel; however, because each reference address requires dedicated logic gates, this is an expensive implementation. This approach is typically expanded further through the use of magnitude comparators, which allows the address on the bus to be compared to an entire range of addresses. The problem with magnitude comparators is that a reference address is determined to be greater/equal (or less than) the address on the bus. Although this comparison covers an entire range of addresses, a “greater/equal (or less than)” comparison requires significantly more logic gates than does a single “equals
ot-equals” comparison.
By allowing the user to specify ranges of addresses on which to cause the events when accessed, the user has a considerably more powerful debug tool. However, this implementation requires a large number of gates, often commonly causes speed paths, and is often not well suited to peripheral or ASIC registers which as mapped in memory (since not all registers within a group will have the same events associated with them). What is need is a fast, low-cost means of comparing a bus address against numerous individual addresses simultaneously. This would allow the user to specify what memory-mapped variables, peripheral registers, and/or ASIC registers to cause (or not cause) events on.
SUMMARY OF THE INVENTION
A Page Address Look-up Range RAM is disclosed which allows for individual comparisons to be made on a number of consecutive addresses. The upper bits of the bus address (often representing a “page”) are compared against one or more reference registers to yield one or more “match_high”s. The lower bits of the same bus address are used to look-up the value of “match_low” in a RAM, the bit of interest corresponding to the particular “match-high” reference register. If both the “match_high” and “match_low” events are true, or=1, then the bus address has matched and should cause the event, otherwise not. The most cost effective implementations will have a Look-up RAM with a width of a multiple of 8. This will allow comparison of the bus address against a multiple of individual pages.
One advantage of using a Page Address Look-up RAM is the large number of possible individual comparisons available at relatively low cost. The large number of individual comparisons allow the user to be selective as to what addresses cause (or don't cause) an event.
A second advantage of using a Page Address Look-Up RAM is that, because the lookup RAM can be implemented through memory cells, it can be implemented with less silicon area than one which requires primarily logic gates. Because no magnitude comparator is used, there is less of a speed path.
A third advantage of the using a Page Address Look-up RAM is that it allows multiple comparisons to be done, without requiring dedicated logic gates for every single reference address.
A fourth advantage of using a Page Address Look-up RAM is that it allows for individual addresses to be compared against, rather than an entire range, which is often desired for memory-mapped variables, peripheral registers, etc.
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