Pad structure with parasitic MOS transistor for use with semicon

Details Pad structure with parasitic MOS transistor for use with semicon Pad structure with parasitic MOS transistor for use with semicon

1993-07-23

1996-05-14

Crane, Sara W.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257357, H01L 2362

Patent

active

055170480

ABSTRACT:
An ESD protection device for protecting semiconductor devices from electrostatic discharge includes a metal pad of the semiconductor device, a first charge sink, and a first MOS transistor. The first MOS transistor is placed under the metal pad. The first MOS transistor is coupled as a switch between the first charge sink and the metal pad. In addition, the metal pad operates as a gate of the first MOS transistor. Upon static electricity of a high magnitude of voltage being placed on the metal pad, the first MOS transistor turns on and the static electricity is discharged to the first charge sink.

REFERENCES:
patent: 4789917 (1988-12-01), Miller
patent: 4929350 (1989-05-01), Miller
patent: 4937471 (1990-06-01), Park et al.
patent: 5151767 (1992-09-01), Wong
patent: 5329143 (1994-07-01), Chan et al.
Patent Abstracts of Japan vol. 14, No. 194 (E-0919) 20 Apr. 1990 & JP, A, 02049960 (NCC) 9 Feb. 1990.
Patent Abstracts of Japan vol. 16, No. 130 (E-1184) 2 Apr. 1992 & JP, A, 03291970 (Fujitsu) 24 Dec. 1991.
Ajiki Tsuneo, "Reliability of IC Device", Nikkagiren Publishing, k.k., Jul. 1988 (third printing, May 1991), p. 282.
Toshiba IC Reliability Handbook, Nov. 1987, p. 130.

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