Pad calibration circuit with on-chip resistor

Details Pad calibration circuit with on-chip resistor Pad calibration circuit with on-chip resistor

2001-05-07

2003-05-20

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

C326S032000, C326S034000, C326S087000

Reexamination Certificate

active

06566904

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention pertains in general to calibration circuits for an I/O pad on an integrated circuit and, more particularly, to a calibration circuit for an I/O pad that interfaces with a transmission line in an Ethernet system, which calibration circuit calibrates an on-chip resistor that is utilized to source terminate the transmission line.
BACKGROUND OF THE INVENTION
Data traffic between remote stations in various networks has seen a steady increase over the last decade or so. As the data traffic increases, so does the need for bandwidth, although present network interconnections have some difficulty in keeping up with the bandwidth demand. One of these networks is Ethernet and the highest data rate is that associated with the 1000BT Ethernet controllers that allow up to a Gigabit of data to be transferred per second. However, the speed of these controllers present new problems to the designer that must be solved when interfacing with the existing network media, such as a twisted wire transmission pair, coaxial cable or optical fiber, and when interfacing with other integrated circuits on the controller, such as between the physical layer device (PHY) and the Media Access Controller (MAC).
In a typical 1000BT Ethernet controller, there is typically provided a PHY integrated circuit for interfacing between the network media, i.e., a twisted wire pair, and the MAC. This typically involves a transmission line disposed between pins on the PHY and the MAC for receiving incoming data and transmitting outgoing data, in addition to carrying various clock signals between the two integrated circuits. Therefore, each driver on the Ethernet controller must interface with the impedance of the transmission line when carrying data from the PHY to the MAC and from the MAC to the PHY, and present thereto an equal impedance to minimize reflections and provide a match therefor. This can present a problem, in that the output impedance of the driver is typically relatively low compared to the impedance of the transmission line between the PHY and the MAC. One method for matching the driver to the impedance of the transmission line is to utilize an external resistance disposed between the driver and the transmission line. By adding a series resistance between the driver and the transmission line, the overall output impedance presented to the transmission line would be adjusted to 50 ohms, and therefore, this would provide a match, thus reducing reflections. The problem with source terminating the pad when utilizing an integrated circuit is the fact that the resistor must be fabricated on the integrated circuit, this typically requiring some type of polycrystalline resistor. These types of resistors are prone to process and temperature variations. Therefore, they would require some type of process and temperature compensation, and some type of trimming in order to account for the process variations.
SUMMARY OF THE INVENTION
The present invention disclosed and claimed herein, in one aspect thereof, comprises an integrated circuit with an impedance terminated output terminal. A source is provided for sourcing current to the output terminal of the integrated circuit, which output terminal interfaces with a load having a finite impedance associated therewith. An on-chip source impedance is disposed internal to the integrated circuit and between said source and the output terminal to define the input impedance of the output terminal.


REFERENCES:
patent: 5194765 (1993-03-01), Dunlop et al.
patent: 5243229 (1993-09-01), Gabara et al.
patent: 5298800 (1994-03-01), Dunlop et al.
patent: 5955894 (1999-09-01), Vishwanthaiah et al.
patent: 6127862 (2000-10-01), Kawasumi
patent: 6380758 (2002-04-01), Hsu et al.
Gabara, Thaddeus J. Knauer, Scott C.; “Digitally Adjustable Resistors in CMOS for High-Performance Applications,” IEEE Journal of Solid-State Circuits, 8/92, pp. 1176-1185, vol. 27, No. 8.

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